1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/os/kernelhwsrv/bsptemplate/asspandvariant/template_assp/i2spsl.cpp Fri Jun 15 03:10:57 2012 +0200
1.3 @@ -0,0 +1,533 @@
1.4 +// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
1.5 +// All rights reserved.
1.6 +// This component and the accompanying materials are made available
1.7 +// under the terms of the License "Eclipse Public License v1.0"
1.8 +// which accompanies this distribution, and is available
1.9 +// at the URL "http://www.eclipse.org/legal/epl-v10.html".
1.10 +//
1.11 +// Initial Contributors:
1.12 +// Nokia Corporation - initial contribution.
1.13 +//
1.14 +// Contributors:
1.15 +//
1.16 +// Description:
1.17 +// template\template_assp\i2spsl.cpp
1.18 +//
1.19 +//
1.20 +
1.21 +#include <kernel/kernel.h>
1.22 +#include <drivers/i2s.h>
1.23 +
1.24 +// TO DO: (mandatory)
1.25 +// If your ASIC supports multiple I2S interfaces you need to design the most appropriate way of handling that:
1.26 +// - it is possible that a common register per function is used on some of the functions, e.g. a single Control
1.27 +// Register is used to select Master/Slave roles, Transmitter/Receiver/Bidirectional/Controller mode, word
1.28 +// length etc for all interfaces supported. In this case handling the interface Id typically involves the use
1.29 +// of shifts and masks;
1.30 +// - some functions can never be covered by a single register common to all interfaces (e.g. the transmit/receive
1.31 +// registers). Even if it was possible to use single registers to cover a number of interfaces the ASIC designer
1.32 +// may decide to have separate registers for each interface. In this case each of the below APIs could be implemented
1.33 +// as a switch(interface)-case and then use different sets of register addresses for each interface. This model makes
1.34 +// sense when a single developer is responsible for implementing all interfaces (typically in a single source file).
1.35 +// - when each interface is implemented independently it makes sense to separate the implementation into a interface
1.36 +// independent layer and a specific layer and redirect each call from the interface independent layer into the relavant
1.37 +// interface. This is exemplified with the NAVIENGINE implementation.
1.38 +//
1.39 +
1.40 +enum TIs2Panic
1.41 + {
1.42 + ECalledFromIsr
1.43 + };
1.44 +
1.45 +EXPORT_C TInt I2s::ConfigureInterface(TInt aInterfaceId, TDes8* aConfig)
1.46 +//
1.47 +// Configures the interface: its type (Transmitter/Receiver/Bidirectional/Controller) and the role played by it (Master/Slave).
1.48 +//
1.49 + {
1.50 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.51 + // TO DO: (mandatory)
1.52 + //
1.53 + // Extracts the configuration information from aConfig and programs the relevant registers for the interface identified by aInterfaceId.
1.54 + //
1.55 + return KErrNone;
1.56 + }
1.57 +
1.58 +EXPORT_C TInt I2s::GetInterfaceConfiguration(TInt aInterfaceId, TDes8& aConfig)
1.59 +//
1.60 +// Reads the current configuration.
1.61 +//
1.62 + {
1.63 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.64 + // TO DO: (optional)
1.65 + //
1.66 + // Reads the relevant registers and assembles configuration information to be returned in aConfig.
1.67 + //
1.68 + return KErrNotSupported;
1.69 + }
1.70 +
1.71 +EXPORT_C TInt I2s::SetSamplingRate(TInt aInterfaceId, TI2sSamplingRate aSamplingRate)
1.72 +//
1.73 +// Sets the sampling rate.
1.74 +//
1.75 + {
1.76 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.77 + // TO DO: (mandatory)
1.78 + //
1.79 + // Programs the required sampling rate onto the relevant registers for the interface identified by aInterfaceId .
1.80 + //
1.81 + return KErrNone;
1.82 + }
1.83 +
1.84 +EXPORT_C TInt I2s::GetSamplingRate(TInt aInterfaceId, TInt& aSamplingRate)
1.85 +//
1.86 +// Reads the sampling rate.
1.87 +//
1.88 + {
1.89 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.90 + // TO DO: (optional)
1.91 + //
1.92 + // Reads the relevant registers to obtain the currently programmed sampling rate to be returned in aSamplingRate.
1.93 + //
1.94 + return KErrNotSupported;
1.95 + }
1.96 +
1.97 +EXPORT_C TInt I2s::SetFrameLengthAndFormat(TInt aInterfaceId, TI2sFrameLength aFrameLength, TInt aLeftFramePhaseLength)
1.98 +//
1.99 +// Sets the frame format.
1.100 +//
1.101 + {
1.102 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.103 + // TO DO: (mandatory)
1.104 + //
1.105 + // If the interface only allows symmetrical frame lengths this function programs the required
1.106 + // overall frame length onto the relevant registers for the interface identified by aInterfaceId.
1.107 + // In this case aLeftFramePhaseLength can be ignored.
1.108 + // If the interface supports asymmetrical frame lengths, calculates the righ frame length as
1.109 + // (aFrameLength-aLeftFramePhaseLength) and programs both the left and right frame lengths onto
1.110 + // the relevant registers for the interface identified by aInterfaceId.
1.111 + //
1.112 + return KErrNone;
1.113 + }
1.114 +
1.115 +EXPORT_C TInt I2s::GetFrameFormat(TInt aInterfaceId, TInt& aLeftFramePhaseLength, TInt& aRightFramePhaseLength)
1.116 +//
1.117 +// Reads the frame format.
1.118 +//
1.119 + {
1.120 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.121 + // TO DO: (optional)
1.122 + //
1.123 + // If the interface only supports symmetrical frame lengths this function reads the relevant registers to obtain
1.124 + // the currently programmed overall frame length for the interface identified by aInterfaceId: it returns the same
1.125 + // value in both aLeftFramePhaseLength and aRightFramePhaseLength (that is overal frame length/2).
1.126 + // If the interface supports asymmetrical frame lngths, reads the appropriate registers to obtain the left and right
1.127 + // frame lengths to be returned in aLeftFramePhaseLength and aRightFramePhaseLength.
1.128 + //
1.129 + return KErrNotSupported;
1.130 + }
1.131 +
1.132 +EXPORT_C TInt I2s::SetSampleLength(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sSampleLength aSampleLength)
1.133 +//
1.134 +// Sets the sample length for a frame phase.
1.135 +//
1.136 + {
1.137 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.138 + // TO DO: (mandatory)
1.139 + //
1.140 + // Programs the required sample length for the frame phase specified (left or right) onto the relevant registers for the interface identified by aInterfaceId .
1.141 + //
1.142 + return KErrNone;
1.143 + }
1.144 +
1.145 +EXPORT_C TInt I2s::GetSampleLength(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aSampleLength)
1.146 +//
1.147 +// Reads the sample length for a frame phase.
1.148 +//
1.149 + {
1.150 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.151 + // TO DO: (optional)
1.152 + //
1.153 + // Reads the relevant registers to obtain the sample length for the frame phase specified (left or right) to be returned in aSampleLength.
1.154 + //
1.155 + return KErrNotSupported;
1.156 + }
1.157 +
1.158 +EXPORT_C TInt I2s::SetDelayCycles(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aDelayCycles)
1.159 +//
1.160 +// Sets the number of delay cycles for a frame phase.
1.161 +//
1.162 + {
1.163 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.164 + // TO DO: (optional)
1.165 + //
1.166 + // If the interface supports delaying the start of a frame by a specified number of bit clock cycles this function programs the required
1.167 + // delay cycles for the frame phase specified (left or right) onto the relevant registers for the interface identified by aInterfaceId .
1.168 + //
1.169 + return KErrNotSupported;
1.170 + }
1.171 +
1.172 +EXPORT_C TInt I2s::GetDelayCycles(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aDelayCycles)
1.173 +//
1.174 +// Reads the sample length for a frame phase.
1.175 +//
1.176 + {
1.177 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.178 + // TO DO: (optional)
1.179 + //
1.180 + // If the interface supports delaying the start of a frame by a specified number of bit clock cycles this function reads the relevant
1.181 + // registers to obtain the number of delay cycles for the frame phase specified (left or right) to be returned in aSampleLength.
1.182 + //
1.183 + return KErrNotSupported;
1.184 + }
1.185 +
1.186 +EXPORT_C TInt I2s::ReadReceiveRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aData)
1.187 +//
1.188 +// Reads the receive data register for a frame phase.
1.189 +//
1.190 + {
1.191 + // TO DO: (mandatory)
1.192 + //
1.193 + // Reads the contents of the receive register to obtain the data for the frame phase specified (left or right) to be returned in aData.
1.194 + // If the implementation only supports a single receive register for both frame phases, the aFramePhase argument can be ignored and the
1.195 + // function returns the contents of the single register.
1.196 + //
1.197 + return KErrNone;
1.198 + }
1.199 +
1.200 +EXPORT_C TInt I2s::WriteTransmitRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aData)
1.201 +//
1.202 +// Writes to the transmit data register for a frame phase.
1.203 +//
1.204 + {
1.205 + // TO DO: (mandatory)
1.206 + //
1.207 + // Writes the Audio data passed in aData to the transmit register for the frame phase specified (left or right) for the interface identified
1.208 + // by aInterfaceId.
1.209 + // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored and the
1.210 + // function writes to the single register.
1.211 + //
1.212 + return KErrNone;
1.213 + }
1.214 +
1.215 +EXPORT_C TInt I2s::ReadTransmitRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aData)
1.216 +//
1.217 +// Reads the transmit data register for a frame phase.
1.218 +//
1.219 + {
1.220 + // TO DO: (optional)
1.221 + //
1.222 + // Reads the contents of the transmit register to obtain the data for the frame phase specified (left or right) to be returned in aData.
1.223 + // If the implementation only supports a single receive register for both frame phases, the aFramePhase argument can be ignored and the
1.224 + // function returns the contents of the single transmit register.
1.225 + // If the implementation does not support reading the transmit register simply return KErrNotSupported.
1.226 + //
1.227 + return KErrNotSupported;
1.228 + }
1.229 +
1.230 +EXPORT_C TInt I2s::ReadRegisterModeStatus(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aFlags)
1.231 +//
1.232 +// Reads the Register PIO access mode status flags for a frame phase.
1.233 +//
1.234 + {
1.235 + // TO DO: (optional)
1.236 + //
1.237 + // If the implementation supports Register PIO mode this function reads the contents of the Register PIO mode status register to obtain
1.238 + // the status flags for the frame phase specified (left or right) to be returned in aFlags. The mode flags are described in TI2sFlags.
1.239 + // If the implementation does not support Register PIO mode simply return KErrNotSupported.
1.240 + //
1.241 + return KErrNotSupported;
1.242 + }
1.243 +
1.244 +EXPORT_C TInt I2s::EnableRegisterInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt)
1.245 +//
1.246 +// Enables Register PIO access mode related interrupts for a frame phase.
1.247 +//
1.248 + {
1.249 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.250 + // TO DO: (optional)
1.251 + //
1.252 + // If the implementation supports Register PIO mode this function enables the mode interrupts specified by the bitmask aInterrupt
1.253 + // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" enable the
1.254 + // corresponding interrupts
1.255 + // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored.
1.256 + // If the implementation does not support Register PIO mode simply return KErrNotSupported.
1.257 + //
1.258 + return KErrNotSupported;
1.259 + }
1.260 +
1.261 +EXPORT_C TInt I2s::DisableRegisterInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt)
1.262 +//
1.263 +// Disables Register PIO access mode related interrupts for a frame phase.
1.264 +//
1.265 + {
1.266 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.267 + // TO DO: (optional)
1.268 + //
1.269 + // If the implementation supports Register PIO mode this function disables the mode interrupts specified by the bitmask aInterrupt
1.270 + // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" disable the
1.271 + // corresponding interrupts
1.272 + // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored.
1.273 + // If the implementation does not support Register PIO mode simply return KErrNotSupported.
1.274 + //
1.275 + return KErrNotSupported;
1.276 + }
1.277 +
1.278 +EXPORT_C TInt I2s::IsRegisterInterruptEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled)
1.279 +//
1.280 +// Reads the Register PIO access mode interrupt mask for a frame phase.
1.281 +//
1.282 + {
1.283 + // TO DO: (optional)
1.284 + //
1.285 + // If the implementation supports Register PIO mode this function reads the relevant registers to find out which mode interrupts
1.286 + // are enabled for the frame phase specified (left or right), and returns a bitmask of enabled interrupts in aEnabled.
1.287 + // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled
1.288 + // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored.
1.289 + // If the implementation does not support Register PIO mode simply return KErrNotSupported.
1.290 + //
1.291 + return KErrNotSupported;
1.292 + }
1.293 +
1.294 +EXPORT_C TInt I2s::EnableFIFO(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aFifoMask)
1.295 +//
1.296 +// Enables receive and/or transmit FIFO on a per frame phase basis.
1.297 +//
1.298 + {
1.299 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.300 + // TO DO: (optional)
1.301 + //
1.302 + // If the implementation supports FIFO mode this function enables the FIFOs for the directions specified in the bitmask aFifoMask
1.303 + // (Transmit and/or Receive) for the frame phase specified (left or right). Bits set to "1" enable the corresponding FIFO.
1.304 + // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aFifoMask can be ignored.
1.305 + // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored.
1.306 + //
1.307 + return KErrNotSupported;
1.308 + }
1.309 +
1.310 +EXPORT_C TInt I2s::DisableFIFO(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aFifoMask)
1.311 +//
1.312 +// Disables receive and/or transmit FIFO on a per frame phase basis.
1.313 +//
1.314 + {
1.315 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.316 + // TO DO: (optional)
1.317 + //
1.318 + // If the implementation supports FIFO mode this function disables the FIFOs for the directions specified in the bitmask aFifoMask
1.319 + // (Transmit and/or Receive) for the frame phase specified (left or right). Bits set to "1" disable the corresponding FIFO.
1.320 + // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aFifoMask can be ignored.
1.321 + // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored.
1.322 + //
1.323 + return KErrNotSupported;
1.324 + }
1.325 +
1.326 +EXPORT_C TInt I2s::IsFIFOEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled)
1.327 +//
1.328 +// Reads the enabled state of a frame phase's FIFOs.
1.329 +//
1.330 + {
1.331 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.332 + // TO DO: (optional)
1.333 + //
1.334 + // If the implementation supports FIFO mode this function reads the relevant registers to find out which FIFOs
1.335 + // are enabled (Transmit and/or Receive FIFO) for the frame phase specified (left or right), and returns a bitmask of enabled FIFOs in aEnabled.
1.336 + // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled
1.337 + // If the implementation has a combined receive/transmit FIFO then aEnabled should have both Rx and Tx bits set when the FIFO is enabled.
1.338 + // If the implementation only supports a single FIFO for both frame phases then aFramePhase is ignore.
1.339 + //
1.340 + return KErrNotSupported;
1.341 + }
1.342 +
1.343 +EXPORT_C TInt I2s::SetFIFOThreshold(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sDirection aDirection, TInt aThreshold)
1.344 +//
1.345 +// Sets the receive or transmit FIFO threshold on a per frame phase basis.
1.346 +//
1.347 + {
1.348 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.349 + // TO DO: (optional)
1.350 + //
1.351 + // If the implementation supports FIFO mode this function sets the FIFO threshold for the direction specified in aDirection
1.352 + // (Transmit or Receive) for the frame phase specified (left or right).
1.353 + // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aDirection can be ignored.
1.354 + // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored.
1.355 + //
1.356 + return KErrNotSupported;
1.357 + }
1.358 +
1.359 +EXPORT_C TInt I2s::ReadFIFOModeStatus(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aFlags)
1.360 +//
1.361 +// Reads the FIFO PIO access mode status flags for a frame phase.
1.362 +//
1.363 + {
1.364 + // TO DO: (optional)
1.365 + //
1.366 + // If the implementation supports FIFO mode this function reads the contents of the FIFO mode status register to obtain
1.367 + // the status flags for the frame phase specified (left or right) to be returned in aFlags. The mode flags are described in TI2sFlags.
1.368 + // A bit set to "1" indicates the condition described by the corresponding flag is occurring.
1.369 + // If the implementation has a combined receive/transmit FIFO then aFlags should be set according to which operation (receive/transmit) is
1.370 + // currently undergoing.
1.371 + // If the implementation only supports a single FIFO for both frame phases then aFramePhase is ignored.
1.372 + //
1.373 + return KErrNotSupported;
1.374 + }
1.375 +
1.376 +EXPORT_C TInt I2s::EnableFIFOInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt)
1.377 +//
1.378 +// Enables FIFO related interrupts for a frame phase.
1.379 +//
1.380 + {
1.381 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.382 + // TO DO: (optional)
1.383 + //
1.384 + // If the implementation supports FIFO mode this function enables the mode interrupts specified by the bitmask aInterrupt
1.385 + // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" enable the
1.386 + // corresponding interrupts
1.387 + // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored.
1.388 + //
1.389 + return KErrNotSupported;
1.390 + }
1.391 +
1.392 +EXPORT_C TInt I2s::DisableFIFOInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt)
1.393 +//
1.394 +// Disables FIFO related interrupts for a frame phase.
1.395 +//
1.396 + {
1.397 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.398 + // TO DO: (optional)
1.399 + //
1.400 + // If the implementation supports FIFO mode this function disables the mode interrupts specified by the bitmask aInterrupt
1.401 + // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" disable the
1.402 + // corresponding interrupts
1.403 + // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored.
1.404 + //
1.405 + return KErrNotSupported;
1.406 + }
1.407 +
1.408 +EXPORT_C TInt I2s::IsFIFOInterruptEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled)
1.409 +//
1.410 +// Reads the FIFO interrupt masks for a frame phase.
1.411 +//
1.412 + {
1.413 + // TO DO: (optional)
1.414 + //
1.415 + // If the implementation supports FIFO mode this function reads the relevant registers to find out which mode interrupts
1.416 + // are enabled for the frame phase specified (left or right), and returns a bitmask of enabled interrupts in aEnabled.
1.417 + // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled
1.418 + // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored.
1.419 + //
1.420 + return KErrNotSupported;
1.421 + }
1.422 +
1.423 +EXPORT_C TInt I2s::ReadFIFOLevel(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sDirection aDirection, TInt& aLevel)
1.424 +//
1.425 +// Reads the receive or transmit FIFO current level on a per frame phase basis.
1.426 +//
1.427 + {
1.428 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.429 + // TO DO: (optional)
1.430 + //
1.431 + // If the implementation supports FIFO mode this function reads the relevant registers to find out the current FIFO level
1.432 + // for the direction specified and for the frame phase specified (left or right), and returns it in aLevel.
1.433 + // If the implementation has a combined receive/transmit FIFO then aDirection is ignored.
1.434 + // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored.
1.435 + //
1.436 + return KErrNotSupported;
1.437 + }
1.438 +
1.439 +EXPORT_C TInt I2s::EnableDMA(TInt aInterfaceId, TInt aFifoMask)
1.440 +//
1.441 +// Enables receive and/or transmit DMA.
1.442 +//
1.443 + {
1.444 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.445 + // TO DO: (optional)
1.446 + //
1.447 + // If the implementation supports FIFO DMA mode this function enables DMA in the directions (Transmit and/or Receive) specified
1.448 + // by the bitmask aFifoMask for the frame phase specified (left or right). Bits set to "1" enable DMA.
1.449 + // If the implementation has a combined receive/transmit FIFO then aFifoMask can be ignored.
1.450 + //
1.451 + return KErrNotSupported;
1.452 + }
1.453 +
1.454 +EXPORT_C TInt I2s::DisableDMA(TInt aInterfaceId, TInt aFifoMask)
1.455 +//
1.456 +// Disables receive and/or transmit DMA.
1.457 +//
1.458 + {
1.459 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.460 + // TO DO: (optional)
1.461 + //
1.462 + // If the implementation supports FIFO DMA mode this function disables DMA in the directions (Transmit and/or Receive) specified
1.463 + // by the bitmask aFifoMask for the frame phase specified (left or right). Bits set to "1" disable DMA.
1.464 + // If the implementation has a combined receive/transmit FIFO then aFifoMask can be ignored.
1.465 + //
1.466 + return KErrNotSupported;
1.467 + }
1.468 +
1.469 +EXPORT_C TInt I2s::IsDMAEnabled(TInt aInterfaceId, TInt& aEnabled)
1.470 +//
1.471 +// Reads the enabled state of DMA.
1.472 +//
1.473 + {
1.474 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.475 + // TO DO: (optional)
1.476 + //
1.477 + // If the implementation supports FIFO DMA mode this function reads the relevant registers to find out which directions
1.478 + // (Transmit and/or Receive) DMA is enabled for the frame phase specified (left or right), and returns a bitmask of enabled
1.479 + // directions in aEnabled. A bit set to "1" indicates DMA is enabled for the corresponding direction.
1.480 + // If the implementation has a combined receive/transmit FIFO then aEnabled should have both Rx and Tx bits set when the DMA is enabled.
1.481 + //
1.482 + return KErrNotSupported;
1.483 + }
1.484 +
1.485 +EXPORT_C TInt I2s::Start(TInt aInterfaceId, TInt aDirection)
1.486 +//
1.487 +// Starts data transmission and/or data reception unless interface is a Controller;
1.488 +// if the device is also a Master, starts generation of data synchronisation signals.
1.489 +//
1.490 + {
1.491 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.492 + // TO DO: (optional)
1.493 + //
1.494 + // Programs the appropriate registers to start operation in the direction specified by aDirection.
1.495 + // Should check if the interface has been configured coherently.
1.496 + //
1.497 + return KErrNotSupported;
1.498 + }
1.499 +
1.500 +EXPORT_C TInt I2s::Stop(TInt aInterfaceId, TInt aDirection)
1.501 +//
1.502 +// Stops data transmission and/or data reception;
1.503 +// if device is also a Master, stops generation of data synchronisation signals.
1.504 +//
1.505 + {
1.506 + __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr));
1.507 + // TO DO: (optional)
1.508 + //
1.509 + // If the interface has been started, programs the appropriate registers to stop operation in the direction specified by aDirection.
1.510 + //
1.511 + return KErrNotSupported;
1.512 + }
1.513 +
1.514 +EXPORT_C TInt I2s::IsStarted(TInt aInterfaceId, TI2sDirection aDirection, TBool& aStarted)
1.515 +//
1.516 +// Checks if a transmission or a reception is underway.
1.517 +//
1.518 + {
1.519 + // TO DO: (optional)
1.520 + //
1.521 + // Reads the appropriate registers to check if the interface speficied by aInterfaceId is started in the direction
1.522 + // specified by aDirection. Returns teh result (as TRUE or FALSE) in aStarted.
1.523 + // If the interface is a Controller and a bus operation is underway, ETrue should be returned regardless of aDirection.
1.524 + //
1.525 + return KErrNotSupported;
1.526 + }
1.527 +
1.528 +// dll entry point..
1.529 +DECLARE_STANDARD_EXTENSION()
1.530 + {
1.531 + // TO DO: (optional)
1.532 + //
1.533 + // The Kernel extension entry point: if your interface requires any early intialisation do it here.
1.534 + //
1.535 + return KErrNone;
1.536 + }