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/*
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* Copyright (c) 2007
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* Josep Torra <josep@fluendo.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#if __VFP_FP__
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/*
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** compile with -mcpu=arm1136j-s -mfpu=vfp -mfloat-abi=softfp
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**
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** void vfp_add_f32 (float *d, const float *s1, const float *s2, int n);
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** void vfp_add_f64 (double *d, const double *s1, const double *s2, int n);
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** void vfp_divide_f32 (float *d, const float *s1, const float *s2, int n);
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** void vfp_divide_f64 (double *d, const double *s1, const double *s2, int n);
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** void vfp_multiply_f32 (float *d, const float *s1, const float *s2, int n);
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** void vfp_multiply_f64 (double *d, const double *s1, const double *s2, int n);
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** void vfp_subtract_f32 (float *d, const float *s1, const float *s2, int n);
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** void vfp_subtract_f64 (double *d, const double *s1, const double *s2, int n);
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**
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** d: $r0 | s1: $r1 | s2: $r2 | n: $r3 |
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**
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*/
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#define UNROLL_F32_TEMPLATE(fname,finst) \
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.global vfp_ ## fname ## ; \
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vfp_ ## fname ## : \
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stmdb sp!, {fp, lr}; /* save registers to stack */ \
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ands ip, r3, #7; /* ip = n % 8 */ \
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beq vfp_ ## fname ## _unroll; /* if ip == 0 goto prep_loop2 */ \
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vfp_ ## fname ## _loop1: \
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fldmias r1!, {s0}; \
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fldmias r2!, {s1}; \
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## finst ##s s2, s0, s1; \
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fstmias r0!, {s2}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop1; \
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vfp_ ## fname ## _unroll: /* unroll by 8 */ \
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movs ip, r3, lsr #3; /* ip = n / 8 */ \
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beq vfp_ ## fname ## _end; /* if ip == 0 goto finish */ \
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fmrx lr, fpscr; /* read fpscr register into arm */\
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mov fp, #7; \
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orr fp, lr, fp, lsl #16; /* set vector lenght to 8 */ \
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fmxr fpscr, fp; \
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vfp_ ## fname ## _loop2: \
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fldmias r1!, {s8, s9, s10, s11, s12, s13, s14, s15}; \
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fldmias r2!, {s16, s17, s18, s19, s20, s21, s22, s23}; \
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## finst ##s s24, s8, s16; \
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fstmias r0!, {s24, s25, s26, s27, s28, s29, s30, s31}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop2; \
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fmxr fpscr, lr; /* restore original fpscr */ \
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vfp_ ## fname ## _end: \
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ldmia sp!, {fp, pc}; /* recovering from stack and return */
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#define UNROLL_F64_TEMPLATE(fname,finst) \
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.global vfp_ ## fname ## ; \
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vfp_ ## fname ## : \
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stmdb sp!, {fp, lr}; /* save registers to stack */ \
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ands ip, r3, #3; /* ip = n % 3 */ \
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beq vfp_ ## fname ## _unroll; /* if ip == 0 goto prep_loop2 */ \
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vfp_ ## fname ## _loop1: \
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fldmiad r1!, {d0}; \
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fldmiad r2!, {d1}; \
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## finst ##d d2, d0, d1; \
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fstmiad r0!, {d2}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop1; \
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vfp_ ## fname ## _unroll: /* unroll by 4 */ \
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movs ip, r3, lsr #2; /* ip = n / 4 */ \
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beq vfp_ ## fname ## _end; /* if ip == 0 goto finish */ \
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fmrx lr, fpscr; /* read fpscr register into arm */\
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mov fp, #3; \
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orr fp, lr, fp, lsl #16; /* set vector lenght to 8 */ \
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fmxr fpscr, fp; \
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vfp_ ## fname ## _loop2: \
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fldmiad r1!, {d4, d5, d6, d7}; \
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fldmiad r2!, {d8, d9, d10, d11}; \
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## finst ##d d12, d4, d8; \
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fstmiad r0!, {d12, d13, d14, d15}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop2; \
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fmxr fpscr, lr; /* restore original fpscr */ \
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vfp_ ## fname ## _end: \
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ldmia sp!, {fp, pc}; /* recovering from stack and return */
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.align 2
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UNROLL_F32_TEMPLATE(add_f32,fadd);
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UNROLL_F64_TEMPLATE(add_f64,fadd);
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UNROLL_F32_TEMPLATE(divide_f32,fdiv);
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UNROLL_F64_TEMPLATE(divide_f64,fdiv);
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UNROLL_F32_TEMPLATE(multiply_f32,fmul);
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UNROLL_F64_TEMPLATE(multiply_f64,fmul);
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UNROLL_F32_TEMPLATE(subtract_f32,fsub);
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UNROLL_F64_TEMPLATE(subtract_f64,fsub);
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#undef UNROLL_F32_TEMPLATE
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#undef UNROLL_F64_TEMPLATE
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/*
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**
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** void vfp_scalaradd_f32_ns (float *d, const float *s1, const float *s2_1, int n);
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** void vfp_scalaradd_f64_ns (double *d, const double *s1, const double *s2_1, int n);
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** void vfp_scalarmultiply_f32_ns (float *d, const float *s1, const float *s2_1, int n);
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** void vfp_scalarmultiply_f64_ns (double *d, const double *s1, const double *s2_1, int n);
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**
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** d: $r0 | s1: $r1 | s2_1: $r2 | n: $r3 |
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**
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*/
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#define UNROLL_F32_TEMPLATE(fname,finst) \
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.global vfp_ ## fname ## ; \
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vfp_ ## fname ## : \
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stmdb sp!, {fp, lr}; /* save registers to stack */ \
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fldmias r2, {s1}; /* load scalar value */ \
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ands ip, r3, #7; /* ip = n % 8 */ \
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beq vfp_ ## fname ## _unroll; /* if ip == 0 goto prep_loop2 */ \
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vfp_ ## fname ## _loop1: \
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fldmias r1!, {s0}; \
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## finst ##s s2, s0, s1; \
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fstmias r0!, {s2}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop1; \
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vfp_ ## fname ## _unroll: /* unroll by 8 */ \
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movs ip, r3, lsr #3; /* ip = n / 8 */ \
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beq vfp_ ## fname ## _end; /* if ip == 0 goto finish */ \
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fmrx lr, fpscr; /* read fpscr register into arm */\
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mov fp, #7; \
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orr fp, lr, fp, lsl #16; /* set vector lenght to 8 */ \
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fmxr fpscr, fp; \
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vfp_ ## fname ## _loop2: \
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fldmias r1!, {s8, s9, s10, s11, s12, s13, s14, s15}; \
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## finst ##s s24, s8, s1; \
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fstmias r0!, {s24, s25, s26, s27, s28, s29, s30, s31}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop2; \
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fmxr fpscr, lr; /* restore original fpscr */ \
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vfp_ ## fname ## _end: \
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ldmia sp!, {fp, pc}; /* recovering from stack and return */
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#define UNROLL_F64_TEMPLATE(fname,finst) \
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.global vfp_ ## fname ## ; \
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vfp_ ## fname ## : \
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stmdb sp!, {fp, lr}; /* save registers to stack */ \
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fldmiad r2, {d1}; /* load scalar value */ \
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ands ip, r3, #3; /* ip = n % 3 */ \
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beq vfp_ ## fname ## _unroll; /* if ip == 0 goto prep_loop2 */ \
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vfp_ ## fname ## _loop1: \
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fldmiad r1!, {d0}; \
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## finst ##d d2, d0, d1; \
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fstmiad r0!, {d2}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop1; \
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vfp_ ## fname ## _unroll: /* unroll by 4 */ \
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movs ip, r3, lsr #2; /* ip = n / 4 */ \
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beq vfp_ ## fname ## _end; /* if ip == 0 goto finish */ \
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fmrx lr, fpscr; /* read fpscr register into arm */\
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mov fp, #3; \
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orr fp, lr, fp, lsl #16; /* set vector lenght to 4 */ \
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fmxr fpscr, fp; \
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vfp_ ## fname ## _loop2: \
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fldmiad r1!, {d4, d5, d6, d7}; \
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## finst ##d d12, d4, d1; \
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fstmiad r0!, {d12, d13, d14, d15}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop2; \
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fmxr fpscr, lr; /* restore original fpscr */ \
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vfp_ ## fname ## _end: \
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ldmia sp!, {fp, pc}; /* recovering from stack and return */
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UNROLL_F32_TEMPLATE(scalaradd_f32_ns,fadd);
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UNROLL_F64_TEMPLATE(scalaradd_f64_ns,fadd);
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UNROLL_F32_TEMPLATE(scalarmultiply_f32_ns,fmul);
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UNROLL_F64_TEMPLATE(scalarmultiply_f64_ns,fmul);
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#undef UNROLL_F32_TEMPLATE
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#undef UNROLL_F64_TEMPLATE
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/*
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**
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** void vfp_abs_f32_f32_ns(float *d, const float *s, int n);
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** void vfp_abs_f64_f64_ns(double *d, const double *s, int n);
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** void vfp_negative_f32(float *d, const float *s, int n);
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** void vfp_negative_f64(double *d, const double *s, int n);
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**
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** d: $r0 | s: $r1 | n: $r2 |
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**
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*/
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#define UNROLL_F32_TEMPLATE(fname,finst) \
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.global vfp_ ## fname ## ; \
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vfp_ ## fname ## : \
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sl@0
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stmdb sp!, {fp, lr}; /* save registers to stack */ \
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sl@0
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ands ip, r2, #7; /* ip = n % 8 */ \
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sl@0
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beq vfp_ ## fname ## _unroll; /* if ip == 0 goto prep_loop2 */ \
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vfp_ ## fname ## _loop1: \
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sl@0
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fldmias r1!, {s0}; \
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## finst ##s s2, s0; \
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sl@0
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fstmias r0!, {s2}; \
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subs ip, ip, #1; \
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sl@0
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bne vfp_ ## fname ## _loop1; \
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sl@0
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vfp_ ## fname ## _unroll: /* unroll by 8 */ \
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sl@0
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movs ip, r2, lsr #3; /* ip = n / 8 */ \
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sl@0
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beq vfp_ ## fname ## _end; /* if ip == 0 goto finish */ \
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fmrx lr, fpscr; /* read fpscr register into arm */\
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mov fp, #7; \
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orr fp, lr, fp, lsl #16; /* set vector lenght to 8 */ \
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fmxr fpscr, fp; \
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vfp_ ## fname ## _loop2: \
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fldmias r1!, {s8, s9, s10, s11, s12, s13, s14, s15}; \
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## finst ##s s24, s8; \
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fstmias r0!, {s24, s25, s26, s27, s28, s29, s30, s31}; \
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subs ip, ip, #1; \
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bne vfp_ ## fname ## _loop2; \
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fmxr fpscr, lr; /* restore original fpscr */ \
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sl@0
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237 |
vfp_ ## fname ## _end: \
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sl@0
|
238 |
ldmia sp!, {fp, pc}; /* recovering from stack and return */
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sl@0
|
239 |
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sl@0
|
240 |
#define UNROLL_F64_TEMPLATE(fname,finst) \
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sl@0
|
241 |
.global vfp_ ## fname ## ; \
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sl@0
|
242 |
vfp_ ## fname ## : \
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sl@0
|
243 |
stmdb sp!, {fp, lr}; /* save registers to stack */ \
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sl@0
|
244 |
ands ip, r2, #3; /* ip = n % 3 */ \
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sl@0
|
245 |
beq vfp_ ## fname ## _unroll; /* if ip == 0 goto prep_loop2 */ \
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sl@0
|
246 |
vfp_ ## fname ## _loop1: \
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sl@0
|
247 |
fldmiad r1!, {d0}; \
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sl@0
|
248 |
## finst ##d d2, d0; \
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sl@0
|
249 |
fstmiad r0!, {d2}; \
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sl@0
|
250 |
subs ip, ip, #1; \
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sl@0
|
251 |
bne vfp_ ## fname ## _loop1; \
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|
sl@0
|
252 |
vfp_ ## fname ## _unroll: /* unroll by 4 */ \
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|
sl@0
|
253 |
movs ip, r2, lsr #2; /* ip = n / 4 */ \
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|
sl@0
|
254 |
beq vfp_ ## fname ## _end; /* if ip == 0 goto finish */ \
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|
sl@0
|
255 |
fmrx lr, fpscr; /* read fpscr register into arm */\
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|
sl@0
|
256 |
mov fp, #3; \
|
|
sl@0
|
257 |
orr fp, lr, fp, lsl #16; /* set vector lenght to 4 */ \
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|
sl@0
|
258 |
fmxr fpscr, fp; \
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|
sl@0
|
259 |
vfp_ ## fname ## _loop2: \
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|
sl@0
|
260 |
fldmiad r1!, {d4, d5, d6, d7}; \
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|
sl@0
|
261 |
## finst ##d d12, d4; \
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|
sl@0
|
262 |
fstmiad r0!, {d12, d13, d14, d15}; \
|
|
sl@0
|
263 |
subs ip, ip, #1; \
|
|
sl@0
|
264 |
bne vfp_ ## fname ## _loop2; \
|
|
sl@0
|
265 |
fmxr fpscr, lr; /* restore original fpscr */ \
|
|
sl@0
|
266 |
vfp_ ## fname ## _end: \
|
|
sl@0
|
267 |
ldmia sp!, {fp, pc}; /* recovering from stack and return */
|
|
sl@0
|
268 |
|
|
sl@0
|
269 |
UNROLL_F32_TEMPLATE(abs_f32_f32_ns,fabs);
|
|
sl@0
|
270 |
UNROLL_F64_TEMPLATE(abs_f64_f64_ns,fabs);
|
|
sl@0
|
271 |
|
|
sl@0
|
272 |
UNROLL_F32_TEMPLATE(negative_f32,fneg);
|
|
sl@0
|
273 |
UNROLL_F64_TEMPLATE(negative_f64,fneg);
|
|
sl@0
|
274 |
|
|
sl@0
|
275 |
#undef UNROLL_F32_TEMPLATE
|
|
sl@0
|
276 |
#undef UNROLL_F64_TEMPLATE
|
|
sl@0
|
277 |
#endif
|