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// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32test\mmu\t_pages.cpp
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//
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//
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#include <e32std.h>
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#include <e32std_private.h>
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#include <e32svr.h>
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#include "d_shadow.h"
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RShadow Shadow;
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LOCAL_D TUint Read(TUint anAddr)
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{
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return Shadow.Read(anAddr);
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}
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TUint PageTables = 0;
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TCpu Cpu = ECpuUnknown;
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TInt CpuArc = 0;
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TInt CpuSpecial = 0;
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TUint ControlReg = 0;
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const TUint KXPbitM = 0x800000;
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LOCAL_C void ProcessCBTEX(TDes& aDes, TUint aCb, TUint aTex)
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{
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const TPtrC KTEXCB[9] = {_L("StOr"),_L("ShDv"),_L("WTRA"),_L("WBRA"),_L("NoCa"),_L("Resv"),_L("ImpD"),_L("WBWA"),_L("NSDv")};
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const TPtrC KCacheP[4] = {_L("NoCa"),_L("WBWA"),_L("WTRA"),_L("WBRA")};
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aCb = aCb >> 2;
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TUint texCB = aCb | ((aTex&7) << 2);
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if ((texCB<9) && (CpuArc>5))
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aDes.Append(KTEXCB[texCB]);
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else if ((aTex&4) && (CpuArc>5))
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{
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aDes.Append(KCacheP[aTex&3]);
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aDes.Append(TChar('/'));
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aDes.Append(KCacheP[aCb]);
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}
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else
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{
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if (CpuArc>5)
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{
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if (aTex&4)
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aDes.Append(TChar('1'));
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else
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aDes.Append(TChar('0'));
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if (aTex&2)
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aDes.Append(TChar('1'));
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else
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aDes.Append(TChar('0'));
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if (aTex&1)
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aDes.Append(TChar('1'));
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else
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aDes.Append(TChar('0'));
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}
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else if (CpuSpecial == 2)
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{
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if (aTex==1)
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aDes.Append(TChar('X'));
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else if (aTex==0)
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aDes.Append(TChar('_'));
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else
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aDes.Append(TChar('?'));
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}
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if (aCb & 2)
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aDes.Append(TChar('C'));
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else
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aDes.Append(TChar('_'));
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if (aCb & 1)
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aDes.Append(TChar('B'));
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else
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aDes.Append(TChar('_'));
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}
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}
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LOCAL_C void ProcessXNnGS(TDes& aDes, TUint anGS, TUint aXN)
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{
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if ((ControlReg & KXPbitM))
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{
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aDes.Append(TChar(' '));
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if (aXN )
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aDes.Append(_L("XN "));
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else
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aDes.Append(_L("__ "));
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if (anGS&2 )
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aDes.Append(_L("nG "));
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else
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aDes.Append(_L("__ "));
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if (anGS&1 )
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aDes.Append(TChar('S'));
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else
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aDes.Append(TChar('_'));
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}
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}
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LOCAL_C void ProcessAP(TDes& aDes, TUint aAp)
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{
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const TPtrC KAccessP[7] = {_L(" RWNO"),_L(" RWRO"),_L(" RWRW"),_L(" Rsv0"),_L(" RONO"),_L(" RORO"),_L(" Rsv1")};
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const TPtrC KAccZrP[4] = {_L(" NONO"), _L(" RONO"), _L(" RORO"), _L(" Rsv2")};
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TUint access = aAp & 3;
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TUint apx = (aAp >> 3) & 4;
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if (((ControlReg & 0x300) !=0) && apx)
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{
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aDes.Append(_L(" Rsv3"));
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}
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else
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{
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if ((ControlReg & KXPbitM))
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access |= apx;
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if (access==0)
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aDes.Append(KAccZrP[(ControlReg >> 8) & 3]);
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else
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aDes.Append(KAccessP[access-1]);
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}
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}
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LOCAL_C void ProcessPteSE(TUint aPte, TUint anAddr)
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{
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TUint type=aPte&3;
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TBuf<36> buf;
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switch(type)
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{
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case 0:
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// not present
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break;
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case 1:
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{
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// large page
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TUint phys=aPte & 0xffff0000;
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TUint ap0=(aPte>>4)&3;
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TUint ap1=(aPte>>6)&3;
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TUint ap2=(aPte>>8)&3;
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TUint ap3=(aPte>>10)&3;
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TUint tex=(aPte>>12)&0xf;
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ProcessCBTEX(buf,aPte&0xc,tex);
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ProcessAP(buf,ap0);
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ProcessAP(buf,ap1);
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ProcessAP(buf,ap2);
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ProcessAP(buf,ap3);
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RDebug::Print(_L("\t%08x Lpage: phys=%08x, %S"),anAddr,phys,&buf);
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break;
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}
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case 2:
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{
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// small page
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TUint phys=aPte & 0xfffff000;
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TUint ap0=(aPte>>4)&3;
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TUint ap1=(aPte>>6)&3;
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TUint ap2=(aPte>>8)&3;
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TUint ap3=(aPte>>10)&3;
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ProcessCBTEX(buf,aPte&0xc,0);
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ProcessAP(buf,ap0);
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ProcessAP(buf,ap1);
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ProcessAP(buf,ap2);
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ProcessAP(buf,ap3);
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RDebug::Print(_L("\t%08x Spage: phys=%08x, %S"),anAddr,phys,&buf);
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break;
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}
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case 3:
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{
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// extended small page
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TUint phys=aPte & 0xfffff000;
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TUint ap=(aPte>>4)&3;
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TUint tex=(aPte>>6)&0xf;
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ProcessCBTEX(buf,aPte&0xc,tex);
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ProcessAP(buf,ap);
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RDebug::Print(_L("\t%08x XSpage: phys=%08x, %S"),anAddr,phys,&buf);
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break;
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}
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}
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}
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LOCAL_C void ProcessPteSD(TUint aPte, TUint anAddr)
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{
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if ((aPte&3) != 0)
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{
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TBuf<36> buf;
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TUint ap=(aPte>>4)&23;
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if (aPte&2) // XS-Page
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{
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// extended small page
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TUint phys=aPte & 0xfffff000;
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TUint tex=(aPte>>6)&0x7;
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ProcessCBTEX(buf,aPte&0xc,tex);
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ProcessAP(buf,ap);
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ProcessXNnGS(buf, (aPte>>10)&3, aPte &1);
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RDebug::Print(_L("\t%08x XSpage: phys=%08x, %S"),anAddr,phys,&buf);
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}
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else // L-Page
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{
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// large page
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TUint phys=aPte & 0xffff0000;
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TUint tex=(aPte>>12)&0x7;
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ProcessCBTEX(buf,aPte&0xc,tex);
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ProcessAP(buf,ap);
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ProcessXNnGS(buf, (aPte>>10)&3, (aPte >> 15) &1);
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RDebug::Print(_L("\t%08x Lpage: phys=%08x, %S"),anAddr,phys,&buf);
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}
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}// Else "Fault" - Not Present
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}
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LOCAL_C void ProcessPde(TUint aPde, TUint anAddr)
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{
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TUint type=aPde&3;
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TBuf<24> buf;
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switch(type)
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{
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case 0:
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// not present
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if (aPde)
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RDebug::Print(_L(" Not Present\n"));
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break;
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case 1:
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{
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// page table
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TUint ptphys=aPde & 0xfffffc00;
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TUint domain=(aPde>>5)&15;
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TUint P=(aPde&0x200);
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TUint ptpgphys=ptphys & 0xfffff000;
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TUint ptlin=0;
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TInt i;
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for (i=0; i<256; i++)
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{
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if ((Read(PageTables+i*4)&0xfffff000)==ptpgphys)
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{
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if (ptlin==0)
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ptlin=PageTables+(i<<12)+(ptphys & 0xc00);
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else
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RDebug::Print(_L("WARNING Multiple page tables found! alt = %08x\n"), PageTables+(i<<12)+(ptphys & 0xc00));
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}
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}
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if (ptlin)
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{
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RDebug::Print(_L("%08x page table: phys=%08x, domain %2d, %s, page table lin=%08x"),anAddr,ptphys,domain,P?L"ECC":L"No ECC",ptlin);
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for (i=0; i<256; i++)
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{
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TUint addr=anAddr+(i<<12);
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TUint pte=Read(ptlin+i*4);
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if (ControlReg & KXPbitM)
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ProcessPteSD(pte,addr);
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else
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ProcessPteSE(pte,addr);
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}
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}
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else
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RDebug::Print(_L("%08x page table: phys=%08x, domain %2d, %s, page table not found"),anAddr,ptphys,domain,P?L"ECC":L"No ECC");
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break;
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}
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case 2:
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{
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// section
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TUint phys=aPde & 0xfff00000;
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TUint perm=(aPde>>10)&0x23;
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TUint P=(aPde&0x200);
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TUint domain=(aPde>>5)&15;
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ProcessCBTEX(buf,aPde&0xc,(aPde>>12)&0xf); // tex is bigger on xscale, but bit is masked off later.
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ProcessAP(buf,perm);
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294 |
ProcessXNnGS(buf, (aPde>>16)&3, (aPde>>4)&1);
|
|
sl@0
|
295 |
|
|
sl@0
|
296 |
if ((ControlReg & KXPbitM) && (aPde & 0x40000))
|
|
sl@0
|
297 |
{
|
|
sl@0
|
298 |
domain = (domain << 4) | ((aPde >> 20) &15);
|
|
sl@0
|
299 |
RDebug::Print(_L("%08x Supersectn: phys=%08x, base %4d, %s, %S"),anAddr,phys,domain,P?L"ECC":L"No ECC",&buf);
|
|
sl@0
|
300 |
}
|
|
sl@0
|
301 |
else
|
|
sl@0
|
302 |
{
|
|
sl@0
|
303 |
RDebug::Print(_L("%08x section : phys=%08x, domain %2d, %s, %S"),anAddr,phys,domain,P?L"ECC":L"No ECC",&buf);
|
|
sl@0
|
304 |
}
|
|
sl@0
|
305 |
break;
|
|
sl@0
|
306 |
}
|
|
sl@0
|
307 |
default:
|
|
sl@0
|
308 |
// invalid
|
|
sl@0
|
309 |
RDebug::Print(_L("PDE for %08x invalid, value %08x"),anAddr,aPde);
|
|
sl@0
|
310 |
break;
|
|
sl@0
|
311 |
}
|
|
sl@0
|
312 |
}
|
|
sl@0
|
313 |
|
|
sl@0
|
314 |
const TInt KNotInInvalid = -2;
|
|
sl@0
|
315 |
TInt StartInvalid=KNotInInvalid;
|
|
sl@0
|
316 |
TInt StartInvalidBase=0;
|
|
sl@0
|
317 |
TInt EndInvalidBase=0;
|
|
sl@0
|
318 |
|
|
sl@0
|
319 |
void DisplayNotPresent(TInt aCurrentPd)
|
|
sl@0
|
320 |
{
|
|
sl@0
|
321 |
aCurrentPd--;
|
|
sl@0
|
322 |
if (StartInvalid!=KNotInInvalid) // Display any Invalid ranges.
|
|
sl@0
|
323 |
{
|
|
sl@0
|
324 |
if (StartInvalid == aCurrentPd)
|
|
sl@0
|
325 |
RDebug::Print(_L("\nPage Directory 0x%x: Base=0x%x - Not Present.\n"), StartInvalid, StartInvalidBase);
|
|
sl@0
|
326 |
else
|
|
sl@0
|
327 |
RDebug::Print(_L("\nPage Directorys 0x%x-0x%x: Bases=0x%x-0x%x - Not Present.\n"), StartInvalid, aCurrentPd, StartInvalidBase, EndInvalidBase);
|
|
sl@0
|
328 |
|
|
sl@0
|
329 |
StartInvalid=KNotInInvalid;
|
|
sl@0
|
330 |
}
|
|
sl@0
|
331 |
}
|
|
sl@0
|
332 |
|
|
sl@0
|
333 |
void ProcessPd(TUint aPd)
|
|
sl@0
|
334 |
{
|
|
sl@0
|
335 |
TUint i;
|
|
sl@0
|
336 |
TUint pdSize;
|
|
sl@0
|
337 |
TUint pdBase;
|
|
sl@0
|
338 |
TUint offset;
|
|
sl@0
|
339 |
|
|
sl@0
|
340 |
TInt err = Shadow.GetPdInfo(aPd, pdSize, pdBase, offset);
|
|
sl@0
|
341 |
|
|
sl@0
|
342 |
if (err==KErrNone)
|
|
sl@0
|
343 |
{
|
|
sl@0
|
344 |
DisplayNotPresent(aPd);
|
|
sl@0
|
345 |
|
|
sl@0
|
346 |
if (aPd==KGlobalPageDirectory)
|
|
sl@0
|
347 |
RDebug::Print(_L("Global Page Directory: Base=0x%x, Entries=0x%x, Start index=0x%x\n"), pdBase, pdSize, offset);
|
|
sl@0
|
348 |
else
|
|
sl@0
|
349 |
RDebug::Print(_L("\nPage Directory 0x%x: Base=0x%x, Entries=0x%x %x\n"), aPd, pdBase, pdSize, offset);
|
|
sl@0
|
350 |
|
|
sl@0
|
351 |
if (Cpu == ECpuArm)
|
|
sl@0
|
352 |
{
|
|
sl@0
|
353 |
|
|
sl@0
|
354 |
for (i=0; i<pdSize; i++)
|
|
sl@0
|
355 |
{
|
|
sl@0
|
356 |
TUint addr=(i+offset)<<20;
|
|
sl@0
|
357 |
TUint pde=Read(pdBase+i*4);
|
|
sl@0
|
358 |
ProcessPde(pde,addr);
|
|
sl@0
|
359 |
}
|
|
sl@0
|
360 |
}
|
|
sl@0
|
361 |
else
|
|
sl@0
|
362 |
RDebug::Print(_L("Cannot display pde for this CPU"));
|
|
sl@0
|
363 |
}
|
|
sl@0
|
364 |
else
|
|
sl@0
|
365 |
{ // Dont list all invalid PDs - there are too many.
|
|
sl@0
|
366 |
if (StartInvalid==KNotInInvalid)
|
|
sl@0
|
367 |
{
|
|
sl@0
|
368 |
StartInvalidBase = pdBase;
|
|
sl@0
|
369 |
StartInvalid = aPd;
|
|
sl@0
|
370 |
}
|
|
sl@0
|
371 |
else
|
|
sl@0
|
372 |
{
|
|
sl@0
|
373 |
EndInvalidBase=pdBase;
|
|
sl@0
|
374 |
}
|
|
sl@0
|
375 |
|
|
sl@0
|
376 |
}
|
|
sl@0
|
377 |
}
|
|
sl@0
|
378 |
|
|
sl@0
|
379 |
GLDEF_C TInt E32Main()
|
|
sl@0
|
380 |
{
|
|
sl@0
|
381 |
TUint mmuId=0;
|
|
sl@0
|
382 |
TUint cacheType=0;
|
|
sl@0
|
383 |
|
|
sl@0
|
384 |
|
|
sl@0
|
385 |
|
|
sl@0
|
386 |
TInt r=User::LoadLogicalDevice(_L("D_SHADOW"));
|
|
sl@0
|
387 |
if ((r!=KErrNone) && (r!=KErrAlreadyExists))
|
|
sl@0
|
388 |
User::Panic(_L("T_PAGES0"),r);
|
|
sl@0
|
389 |
r=Shadow.Open();
|
|
sl@0
|
390 |
if (r!=KErrNone)
|
|
sl@0
|
391 |
User::Panic(_L("T_PAGES1"),r);
|
|
sl@0
|
392 |
|
|
sl@0
|
393 |
Shadow.GetMemoryArchitecture(Cpu, ControlReg);
|
|
sl@0
|
394 |
switch (Cpu)
|
|
sl@0
|
395 |
{
|
|
sl@0
|
396 |
case ECpuArm:
|
|
sl@0
|
397 |
{
|
|
sl@0
|
398 |
mmuId=Shadow.MmuId();
|
|
sl@0
|
399 |
TUint implementor= (mmuId>>24);
|
|
sl@0
|
400 |
|
|
sl@0
|
401 |
if (implementor==0x44)
|
|
sl@0
|
402 |
CpuSpecial = 1;
|
|
sl@0
|
403 |
|
|
sl@0
|
404 |
switch ((mmuId>>12)&15)
|
|
sl@0
|
405 |
{
|
|
sl@0
|
406 |
case 0: // Pre-ARM7
|
|
sl@0
|
407 |
if ((mmuId>>4)==0x4156030)
|
|
sl@0
|
408 |
CpuArc = 2;
|
|
sl@0
|
409 |
else if ((mmuId>>8)==0x415606)
|
|
sl@0
|
410 |
CpuArc = 3;
|
|
sl@0
|
411 |
break;
|
|
sl@0
|
412 |
case 7: // Mid-ARM7
|
|
sl@0
|
413 |
CpuArc = 3;
|
|
sl@0
|
414 |
default:// Post-ARM7
|
|
sl@0
|
415 |
TUint arc = (mmuId >>16) &15;
|
|
sl@0
|
416 |
if (arc<3)
|
|
sl@0
|
417 |
{
|
|
sl@0
|
418 |
CpuArc = 4;
|
|
sl@0
|
419 |
if ((implementor==0x69) && (arc==4))
|
|
sl@0
|
420 |
CpuSpecial=1;
|
|
sl@0
|
421 |
}
|
|
sl@0
|
422 |
else if (arc<7)
|
|
sl@0
|
423 |
{
|
|
sl@0
|
424 |
CpuArc = 5;
|
|
sl@0
|
425 |
if ((implementor==0x69) && (arc==5))
|
|
sl@0
|
426 |
CpuSpecial=2;
|
|
sl@0
|
427 |
}
|
|
sl@0
|
428 |
else if (arc==7)
|
|
sl@0
|
429 |
CpuArc = 6;
|
|
sl@0
|
430 |
else
|
|
sl@0
|
431 |
CpuArc = arc;
|
|
sl@0
|
432 |
}
|
|
sl@0
|
433 |
|
|
sl@0
|
434 |
switch (CpuSpecial)
|
|
sl@0
|
435 |
{
|
|
sl@0
|
436 |
case 1:RDebug::Print(_L("\nCPU = ARMv%d (StrongArm), ControlRegister = 0x%x "),CpuArc, ControlReg);
|
|
sl@0
|
437 |
break;
|
|
sl@0
|
438 |
case 2:RDebug::Print(_L("\nCPU = ARMv%d (XScale), ControlRegister = 0x%x "),CpuArc, ControlReg);
|
|
sl@0
|
439 |
break;
|
|
sl@0
|
440 |
default:
|
|
sl@0
|
441 |
if (CpuArc<7)
|
|
sl@0
|
442 |
RDebug::Print(_L("\nCPU = ARMv%d, ControlRegister = 0x%x "),CpuArc, ControlReg);
|
|
sl@0
|
443 |
else
|
|
sl@0
|
444 |
RDebug::Print(_L("\nCPU = ARM (#%d), ControlRegister = 0x%x "),CpuArc, ControlReg);
|
|
sl@0
|
445 |
}
|
|
sl@0
|
446 |
|
|
sl@0
|
447 |
RDebug::Print(_L("(MMU=%d, Alignment Checking=%d, Write Buffer=%d, System Protection=%d, "),
|
|
sl@0
|
448 |
ControlReg & 1,(ControlReg>>1)&1,(ControlReg>>3)&1, (ControlReg>>8)&1);
|
|
sl@0
|
449 |
|
|
sl@0
|
450 |
if (ControlReg & KXPbitM)
|
|
sl@0
|
451 |
RDebug::Print(_L("ROM Protection=%d, Subpages Disabled, Exception Endian=%d)\n"), (ControlReg>>9)&1, (ControlReg>>25)&1);
|
|
sl@0
|
452 |
else
|
|
sl@0
|
453 |
RDebug::Print(_L("ROM Protection=%d, Subpages Enabled, Exception Endian=%d)\n"), (ControlReg>>9)&1, (ControlReg>>25)&1);
|
|
sl@0
|
454 |
|
|
sl@0
|
455 |
RDebug::Print(_L("MMU ID=%08X"),mmuId);
|
|
sl@0
|
456 |
|
|
sl@0
|
457 |
|
|
sl@0
|
458 |
|
|
sl@0
|
459 |
cacheType=Shadow.CacheType();
|
|
sl@0
|
460 |
RDebug::Print(_L("CACHE TYPE=%08X"),cacheType);
|
|
sl@0
|
461 |
break;
|
|
sl@0
|
462 |
|
|
sl@0
|
463 |
}
|
|
sl@0
|
464 |
|
|
sl@0
|
465 |
case ECpuX86:
|
|
sl@0
|
466 |
RDebug::Print(_L("\nCPU = x86\n"));
|
|
sl@0
|
467 |
break;
|
|
sl@0
|
468 |
case ECpuUnknown:
|
|
sl@0
|
469 |
default:
|
|
sl@0
|
470 |
RDebug::Print(_L("\nCPU = Unknown, Flags = 0x%x\n"), ControlReg);
|
|
sl@0
|
471 |
|
|
sl@0
|
472 |
}
|
|
sl@0
|
473 |
|
|
sl@0
|
474 |
TUint numPages = 0;
|
|
sl@0
|
475 |
TMemModel memModel = Shadow.GetMemModelInfo(PageTables, numPages);
|
|
sl@0
|
476 |
|
|
sl@0
|
477 |
switch (memModel)
|
|
sl@0
|
478 |
{
|
|
sl@0
|
479 |
case EMemModelMoving: RDebug::Print(_L("Moving Memory Model.\n"));
|
|
sl@0
|
480 |
break;
|
|
sl@0
|
481 |
case EMemModelMultiple : RDebug::Print(_L("Multiple Memory Model.\nMax number of PageDirectorys=0x%x.\n"), numPages);
|
|
sl@0
|
482 |
break;
|
|
sl@0
|
483 |
case EMemModelFlexible : RDebug::Print(_L("Flexible Memory Model.\nMax number of PageDirectorys=0x%x.\n"), numPages);
|
|
sl@0
|
484 |
break;
|
|
sl@0
|
485 |
default:
|
|
sl@0
|
486 |
RDebug::Print(_L("Unknown Memory Model.\n"));
|
|
sl@0
|
487 |
return KErrNone;
|
|
sl@0
|
488 |
}
|
|
sl@0
|
489 |
|
|
sl@0
|
490 |
ProcessPd(KGlobalPageDirectory);
|
|
sl@0
|
491 |
|
|
sl@0
|
492 |
if (memModel==2)
|
|
sl@0
|
493 |
{
|
|
sl@0
|
494 |
TUint i;
|
|
sl@0
|
495 |
for (i=0; i<numPages; i++)
|
|
sl@0
|
496 |
{
|
|
sl@0
|
497 |
ProcessPd(i);
|
|
sl@0
|
498 |
}
|
|
sl@0
|
499 |
DisplayNotPresent(numPages);
|
|
sl@0
|
500 |
}
|
|
sl@0
|
501 |
Shadow.Close();
|
|
sl@0
|
502 |
User::FreeLogicalDevice(_L("Shadow"));
|
|
sl@0
|
503 |
return KErrNone;
|
|
sl@0
|
504 |
}
|