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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\common\arm\atomic_ops.h
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//
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//
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#ifdef __OPERATION__
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#undef __OPERATION__
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#undef __OP_RMW1__
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#undef __OP_RMW2__
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#undef __OP_RMW3__
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#undef __OP_SIGNED__
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#undef __TYPE__
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#undef __SIZE_CODE__
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#undef __LDR_INST__
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#undef __LDRS_INST__
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#undef __STR_INST__
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#undef __LDREX_INST__
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#undef __STREX_INST__
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#undef __SIGN_EXTEND__
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#undef __LOG2_DATA_SIZE__
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#undef __OP_LOAD__
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#undef __OP_STORE__
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#undef __OP_SWP__
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#undef __OP_CAS__
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#undef __OP_ADD__
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#undef __OP_AND__
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#undef __OP_IOR__
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#undef __OP_XOR__
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#undef __OP_AXO__
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#undef __OP_TAU__
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#undef __OP_TAS__
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#undef ENSURE_8BYTE_ALIGNMENT
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#else // __OPERATION__
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#if defined(__OP_LOAD__)
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#define __OPERATION__ load
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#elif defined(__OP_STORE__)
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#define __OPERATION__ store
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#elif defined(__OP_SWP__)
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#define __OPERATION__ swp
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#define __OP_RMW1__
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#elif defined(__OP_CAS__)
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#define __OPERATION__ cas
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#elif defined(__OP_ADD__)
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#define __OPERATION__ add
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#define __OP_RMW1__
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#elif defined(__OP_AND__)
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#define __OPERATION__ and
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#define __OP_RMW1__
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#elif defined(__OP_IOR__)
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#define __OPERATION__ ior
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#define __OP_RMW1__
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#elif defined(__OP_XOR__)
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#define __OPERATION__ xor
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#define __OP_RMW1__
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#elif defined(__OP_AXO__)
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#define __OPERATION__ axo
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#define __OP_RMW2__
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#elif defined(__OP_TAU__)
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#define __OPERATION__ tau
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#define __OP_RMW3__
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#elif defined(__OP_TAS__)
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#define __OPERATION__ tas
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#define __OP_RMW3__
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#define __OP_SIGNED__
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#else
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#error Unknown atomic operation
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#endif
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#if __DATA_SIZE__==8
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#define __LOG2_DATA_SIZE__ 3
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#define __SIZE_CODE__ "b"
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#ifdef __CPU_ARM_HAS_LDREX_STREX_V6K
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#define __LDREX_INST__(Rd,Rn) LDREXB(Rd,Rn)
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#define __STREX_INST__(Rd,Rm,Rn) STREXB(Rd,Rm,Rn)
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#endif
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#define __SIGN_EXTEND__(reg) asm("mov "#reg ", "#reg ", lsl #24 "); asm("mov "#reg ", "#reg ", asr #24 ");
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#define __LDR_INST__(cc,args) asm("ldr"#cc "b " args)
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#define __LDRS_INST__(cc,args) asm("ldr"#cc "sb " args)
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#define __STR_INST__(cc,args) asm("str"#cc "b " args)
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#ifdef __OP_SIGNED__
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#define __TYPE__ TInt8
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#else
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#define __TYPE__ TUint8
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#endif
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#elif __DATA_SIZE__==16
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#define __LOG2_DATA_SIZE__ 4
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#define __SIZE_CODE__ "h"
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#ifdef __CPU_ARM_HAS_LDREX_STREX_V6K
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#define __LDREX_INST__(Rd,Rn) LDREXH(Rd,Rn)
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#define __STREX_INST__(Rd,Rm,Rn) STREXH(Rd,Rm,Rn)
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#endif
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#define __SIGN_EXTEND__(reg) asm("mov "#reg ", "#reg ", lsl #16 "); asm("mov "#reg ", "#reg ", asr #16 ");
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#define __LDR_INST__(cc,args) asm("ldr"#cc "h " args)
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#define __LDRS_INST__(cc,args) asm("ldr"#cc "sh " args)
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#define __STR_INST__(cc,args) asm("str"#cc "h " args)
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#ifdef __OP_SIGNED__
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#define __TYPE__ TInt16
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#else
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#define __TYPE__ TUint16
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#endif
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#elif __DATA_SIZE__==32
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#define __LOG2_DATA_SIZE__ 5
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#define __SIZE_CODE__ ""
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#ifdef __CPU_ARM_HAS_LDREX_STREX
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#define __LDREX_INST__(Rd,Rn) LDREX(Rd,Rn)
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#define __STREX_INST__(Rd,Rm,Rn) STREX(Rd,Rm,Rn)
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#endif
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#define __SIGN_EXTEND__(reg)
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#define __LDR_INST__(cc,args) asm("ldr"#cc " " args)
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#define __LDRS_INST__(cc,args) asm("ldr"#cc " " args)
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#define __STR_INST__(cc,args) asm("str"#cc " " args)
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#ifdef __OP_SIGNED__
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#define __TYPE__ TInt32
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#else
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#define __TYPE__ TUint32
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#endif
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#elif __DATA_SIZE__==64
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#define __LOG2_DATA_SIZE__ 6
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#define __SIZE_CODE__ "d"
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#ifdef __CPU_ARM_HAS_LDREX_STREX_V6K
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#define __LDREX_INST__(Rd,Rn) LDREXD(Rd,Rn)
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#define __STREX_INST__(Rd,Rm,Rn) STREXD(Rd,Rm,Rn)
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#endif
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#ifdef __OP_SIGNED__
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#define __TYPE__ TInt64
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#else
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#define __TYPE__ TUint64
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#endif
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#else
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#error Invalid data size
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#endif
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#if (defined(__GNUC__) && (__GNUC__ >= 3)) || defined(__EABI__)
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// Check 8 byte aligned and cause alignment fault if not.
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// Doesn't work if alignment checking is disabled but gives consistent behaviour
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// between processors with ldrexd etc and these hand coded versions.
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#define ENSURE_8BYTE_ALIGNMENT(rAddr) \
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asm("tst r"#rAddr", #0x7 "); \
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asm("orrne r"#rAddr", r"#rAddr", #1 "); \
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asm("ldmne r"#rAddr", {r"#rAddr"} ")
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#else
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// Don't assert on old gcc (arm4) as it is not eabi compliant and this stops
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// kernel booting.
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#define ENSURE_8BYTE_ALIGNMENT(rAddr)
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#endif
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#endif // __OPERATION__
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