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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\common\arm\atomic_64_v6k.h
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// 64 bit atomic operations on V6K processors
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//
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//
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#include "atomic_ops.h"
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#if defined(__OP_LOAD__)
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extern "C" EXPORT_C __NAKED__ __TYPE__ __e32_atomic_load_acq64(const volatile TAny* /*a*/)
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{
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// R0=a
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// return value in R1:R0
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asm("mov r2, r0 ");
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ENSURE_8BYTE_ALIGNMENT(2);
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asm("1: ");
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LDREXD(0,2); // R1:R0 = oldv
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STREXD(3,0,2); // try to write back, R3=0 if success
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asm("cmp r3, #0 ");
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asm("bne 1b "); // failed - retry
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__LOCAL_DATA_MEMORY_BARRIER__(r3);
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__JUMP(,lr);
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}
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#elif defined(__OP_STORE__)
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#define __DO_STORE__ \
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asm("mov r12, r0 "); \
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asm("1: "); \
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LDREXD(0,12); \
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STREXD(1,2,12); \
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asm("cmp r1, #0 "); \
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asm("bne 1b ");
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extern "C" EXPORT_C __NAKED__ __TYPE__ __e32_atomic_store_rel64(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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#ifdef __BARRIERS_NEEDED__ // If no barriers, just fall through to __e32_atomic_store_ord64
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#ifndef __EABI__
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asm("mov r3, r2 ");
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asm("mov r2, r1 ");
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#endif
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// R0=a, R3:R2=v
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// return value in R1:R0 equal to v
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ENSURE_8BYTE_ALIGNMENT(0);
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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__DO_STORE__
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asm("mov r0, r2 ");
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asm("mov r1, r3 ");
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __e32_atomic_store_ord64(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R3:R2=v
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// return value in R1:R0 equal to v
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#ifndef __EABI__
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asm("mov r3, r2 ");
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asm("mov r2, r1 ");
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#endif
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ENSURE_8BYTE_ALIGNMENT(0);
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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__DO_STORE__
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__LOCAL_DATA_MEMORY_BARRIER__(r1);
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asm("mov r0, r2 ");
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asm("mov r1, r3 ");
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__JUMP(,lr);
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}
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#undef __DO_STORE__
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#elif defined(__OP_RMW1__)
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#ifdef __OP_SWP__
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#define __SAVE_REGS__ asm("str r6, [sp, #-4]! ");
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#define __RESTORE_REGS__ asm("ldr r6, [sp], #4 ");
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#define __SOURCE_REG__ 2
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#define __DO_PROCESSING__
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#else
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#define __SAVE_REGS__ asm("stmfd sp!, {r4-r6} ");
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#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r6} ");
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#define __SOURCE_REG__ 4
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#if defined(__OP_ADD__)
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#define __DO_PROCESSING__ asm("adds r4, r0, r2 "); asm("adcs r5, r1, r3 ");
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#elif defined(__OP_AND__)
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#define __DO_PROCESSING__ asm("and r4, r0, r2 "); asm("and r5, r1, r3 ");
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#elif defined(__OP_IOR__)
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#define __DO_PROCESSING__ asm("orr r4, r0, r2 "); asm("orr r5, r1, r3 ");
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#elif defined(__OP_XOR__)
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#define __DO_PROCESSING__ asm("eor r4, r0, r2 "); asm("eor r5, r1, r3 ");
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#endif
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#endif
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#define __DO_RMW1_OP__ \
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asm("mov r12, r0 "); \
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ENSURE_8BYTE_ALIGNMENT(0); \
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asm("1: "); \
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LDREXD(0,12); \
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__DO_PROCESSING__ \
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STREXD(6,__SOURCE_REG__,12); \
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asm("cmp r6, #0 "); \
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asm("bne 1b ");
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,64)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R3:R2=v
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// return value in R1:R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,64)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R3:R2=v
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// return value in R1:R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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#ifndef __EABI__
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asm("mov r3, r2 ");
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asm("mov r2, r1 ");
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#endif
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__SAVE_REGS__
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__DO_RMW1_OP__
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__RESTORE_REGS__
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,64)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R3:R2=v
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// return value in R1:R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,64)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R3:R2=v
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// return value in R1:R0
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#ifndef __EABI__
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asm("mov r3, r2 ");
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asm("mov r2, r1 ");
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#endif
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__SAVE_REGS__
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__DO_RMW1_OP__
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__LOCAL_DATA_MEMORY_BARRIER__(r6);
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__RESTORE_REGS__
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__JUMP(,lr);
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}
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#undef __SAVE_REGS__
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#undef __RESTORE_REGS__
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#undef __DO_RMW1_OP__
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#undef __SOURCE_REG__
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#undef __DO_PROCESSING__
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#elif defined(__OP_CAS__)
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#define __SAVE_REGS__ asm("stmfd sp!, {r4-r7} ");
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#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r7} ");
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#define __DO_CAS_OP__ \
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asm("ldmia r1, {r6-r7} "); \
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ENSURE_8BYTE_ALIGNMENT(0); \
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asm("1: "); \
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LDREXD(4,0); \
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asm("cmp r4, r6 "); \
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asm("cmpeq r5, r7 "); \
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asm("bne 2f "); \
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STREXD(12,2,0); \
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asm("cmp r12, #0 "); \
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asm("bne 1b "); \
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asm("2: "); \
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asm("stmneia r1, {r4-r5} "); \
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asm("movne r0, #0 "); \
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asm("moveq r0, #1 ");
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,rel,64)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R3:R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,rlx,64)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R3:R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__SAVE_REGS__
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__DO_CAS_OP__
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__RESTORE_REGS__
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,ord,64)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R3:R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,acq,64)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R3:R2=v
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// return value in R0
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__SAVE_REGS__
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__DO_CAS_OP__
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__LOCAL_DATA_MEMORY_BARRIER__(r12);
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__RESTORE_REGS__
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__JUMP(,lr);
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}
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#undef __SAVE_REGS__
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#undef __RESTORE_REGS__
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#undef __DO_CAS_OP__
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#elif defined(__OP_AXO__)
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#ifdef __EABI__
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#define __SAVE_REGS__ asm("mov r1, sp "); asm("stmfd sp!, {r4-r8} ");
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#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r8} ");
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#else
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#define __SAVE_REGS__ asm("str r3, [sp, #-4]! "); asm("mov r3, r2 "); asm("mov r2, r1 "); asm("mov r1, sp "); asm("stmfd sp!, {r4-r8} ");
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#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r8,r12} ");
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#endif
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#define __DO_AXO_OP__ \
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asm("ldmia r1, {r4-r5} "); \
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asm("mov r12, r0 "); \
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ENSURE_8BYTE_ALIGNMENT(0); \
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asm("1: "); \
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LDREXD(0,12); \
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asm("and r6, r0, r2 "); \
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asm("and r7, r1, r3 "); \
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asm("eor r6, r6, r4 "); \
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asm("eor r7, r7, r5 "); \
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STREXD(8,6,12); \
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asm("cmp r8, #0 "); \
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asm("bne 1b ");
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#ifdef __EABI__
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,64)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
274 |
#else
|
|
sl@0
|
275 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,64)(int,int,int,int)
|
|
sl@0
|
276 |
#endif
|
|
sl@0
|
277 |
{
|
|
sl@0
|
278 |
// R0=a, R3:R2=u, [SP+4,0]=v
|
|
sl@0
|
279 |
// return value in R1:R0
|
|
sl@0
|
280 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
281 |
__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
|
|
sl@0
|
282 |
#endif
|
|
sl@0
|
283 |
}
|
|
sl@0
|
284 |
|
|
sl@0
|
285 |
#ifdef __EABI__
|
|
sl@0
|
286 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,64)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
287 |
#else
|
|
sl@0
|
288 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,64)(int,int,int,int)
|
|
sl@0
|
289 |
#endif
|
|
sl@0
|
290 |
{
|
|
sl@0
|
291 |
// R0=a, R3:R2=u, [SP+4,0]=v
|
|
sl@0
|
292 |
// return value in R1:R0
|
|
sl@0
|
293 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
294 |
__SAVE_REGS__
|
|
sl@0
|
295 |
__DO_AXO_OP__
|
|
sl@0
|
296 |
__RESTORE_REGS__
|
|
sl@0
|
297 |
__JUMP(,lr);
|
|
sl@0
|
298 |
#endif
|
|
sl@0
|
299 |
}
|
|
sl@0
|
300 |
|
|
sl@0
|
301 |
#ifdef __EABI__
|
|
sl@0
|
302 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,64)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
303 |
#else
|
|
sl@0
|
304 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,64)(int,int,int,int)
|
|
sl@0
|
305 |
#endif
|
|
sl@0
|
306 |
{
|
|
sl@0
|
307 |
// R0=a, R3:R2=u, [SP+4,0]=v
|
|
sl@0
|
308 |
// return value in R1:R0
|
|
sl@0
|
309 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
310 |
__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
|
|
sl@0
|
311 |
#endif
|
|
sl@0
|
312 |
}
|
|
sl@0
|
313 |
|
|
sl@0
|
314 |
#ifdef __EABI__
|
|
sl@0
|
315 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,64)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
316 |
#else
|
|
sl@0
|
317 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,64)(int,int,int,int)
|
|
sl@0
|
318 |
#endif
|
|
sl@0
|
319 |
{
|
|
sl@0
|
320 |
// R0=a, R3:R2=u, [SP+4,0]=v
|
|
sl@0
|
321 |
// return value in R1:R0
|
|
sl@0
|
322 |
__SAVE_REGS__
|
|
sl@0
|
323 |
__DO_AXO_OP__
|
|
sl@0
|
324 |
__LOCAL_DATA_MEMORY_BARRIER__(r8);
|
|
sl@0
|
325 |
__RESTORE_REGS__
|
|
sl@0
|
326 |
__JUMP(,lr);
|
|
sl@0
|
327 |
}
|
|
sl@0
|
328 |
|
|
sl@0
|
329 |
#undef __SAVE_REGS__
|
|
sl@0
|
330 |
#undef __RESTORE_REGS__
|
|
sl@0
|
331 |
#undef __DO_AXO_OP__
|
|
sl@0
|
332 |
|
|
sl@0
|
333 |
|
|
sl@0
|
334 |
#elif defined(__OP_RMW3__)
|
|
sl@0
|
335 |
|
|
sl@0
|
336 |
#ifdef __EABI__
|
|
sl@0
|
337 |
#define __SAVE_REGS__ asm("mov r1, sp "); asm("stmfd sp!, {r4-r10} ");
|
|
sl@0
|
338 |
#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r10} ");
|
|
sl@0
|
339 |
#else
|
|
sl@0
|
340 |
#define __SAVE_REGS__ asm("str r3, [sp, #-4]! "); asm("mov r3, r2 "); asm("mov r2, r1 "); asm("mov r1, sp "); asm("stmfd sp!, {r4-r10} ");
|
|
sl@0
|
341 |
#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r10,r12} ");
|
|
sl@0
|
342 |
#endif
|
|
sl@0
|
343 |
|
|
sl@0
|
344 |
#if defined(__OP_TAU__)
|
|
sl@0
|
345 |
#define __COND_GE__ "cs"
|
|
sl@0
|
346 |
#define __COND_LT__ "cc"
|
|
sl@0
|
347 |
#elif defined(__OP_TAS__)
|
|
sl@0
|
348 |
#define __COND_GE__ "ge"
|
|
sl@0
|
349 |
#define __COND_LT__ "lt"
|
|
sl@0
|
350 |
#endif
|
|
sl@0
|
351 |
|
|
sl@0
|
352 |
#define __DO_RMW3_OP__ \
|
|
sl@0
|
353 |
asm("ldmia r1, {r4-r7} "); \
|
|
sl@0
|
354 |
asm("mov r12, r0 "); \
|
|
sl@0
|
355 |
ENSURE_8BYTE_ALIGNMENT(0); \
|
|
sl@0
|
356 |
asm("1: "); \
|
|
sl@0
|
357 |
LDREXD(0,12); \
|
|
sl@0
|
358 |
asm("subs r8, r0, r2 "); \
|
|
sl@0
|
359 |
asm("sbcs r9, r1, r3 "); \
|
|
sl@0
|
360 |
asm("mov" __COND_GE__ " r8, r4 "); \
|
|
sl@0
|
361 |
asm("mov" __COND_GE__ " r9, r5 "); \
|
|
sl@0
|
362 |
asm("mov" __COND_LT__ " r8, r6 "); \
|
|
sl@0
|
363 |
asm("mov" __COND_LT__ " r9, r7 "); \
|
|
sl@0
|
364 |
asm("adds r8, r8, r0 "); \
|
|
sl@0
|
365 |
asm("adcs r9, r9, r1 "); \
|
|
sl@0
|
366 |
STREXD(10,8,12); \
|
|
sl@0
|
367 |
asm("cmp r10, #0 "); \
|
|
sl@0
|
368 |
asm("bne 1b ");
|
|
sl@0
|
369 |
|
|
sl@0
|
370 |
|
|
sl@0
|
371 |
#ifdef __EABI__
|
|
sl@0
|
372 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,64)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
373 |
#else
|
|
sl@0
|
374 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,64)(int,int,int,int)
|
|
sl@0
|
375 |
#endif
|
|
sl@0
|
376 |
{
|
|
sl@0
|
377 |
// R0=a, R3:R2=t, [SP+4,0]=u, [SP+12,8]=v
|
|
sl@0
|
378 |
// return value in R1:R0
|
|
sl@0
|
379 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
380 |
__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
|
|
sl@0
|
381 |
#endif
|
|
sl@0
|
382 |
}
|
|
sl@0
|
383 |
|
|
sl@0
|
384 |
#ifdef __EABI__
|
|
sl@0
|
385 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,64)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
386 |
#else
|
|
sl@0
|
387 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,64)(int,int,int,int)
|
|
sl@0
|
388 |
#endif
|
|
sl@0
|
389 |
{
|
|
sl@0
|
390 |
// R0=a, R3:R2=t, [SP+4,0]=u, [SP+12,8]=v
|
|
sl@0
|
391 |
// return value in R1:R0
|
|
sl@0
|
392 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
393 |
__SAVE_REGS__
|
|
sl@0
|
394 |
__DO_RMW3_OP__
|
|
sl@0
|
395 |
__RESTORE_REGS__
|
|
sl@0
|
396 |
__JUMP(,lr);
|
|
sl@0
|
397 |
#endif
|
|
sl@0
|
398 |
}
|
|
sl@0
|
399 |
|
|
sl@0
|
400 |
#ifdef __EABI__
|
|
sl@0
|
401 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,64)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
402 |
#else
|
|
sl@0
|
403 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,64)(int,int,int,int)
|
|
sl@0
|
404 |
#endif
|
|
sl@0
|
405 |
{
|
|
sl@0
|
406 |
// R0=a, R3:R2=t, [SP+4,0]=u, [SP+12,8]=v
|
|
sl@0
|
407 |
// return value in R1:R0
|
|
sl@0
|
408 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
409 |
__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
|
|
sl@0
|
410 |
#endif
|
|
sl@0
|
411 |
}
|
|
sl@0
|
412 |
|
|
sl@0
|
413 |
#ifdef __EABI__
|
|
sl@0
|
414 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,64)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
415 |
#else
|
|
sl@0
|
416 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,64)(int,int,int,int)
|
|
sl@0
|
417 |
#endif
|
|
sl@0
|
418 |
{
|
|
sl@0
|
419 |
// R0=a, R3:R2=t, [SP+4,0]=u, [SP+12,8]=v
|
|
sl@0
|
420 |
// return value in R1:R0
|
|
sl@0
|
421 |
__SAVE_REGS__
|
|
sl@0
|
422 |
__DO_RMW3_OP__
|
|
sl@0
|
423 |
__LOCAL_DATA_MEMORY_BARRIER__(r10);
|
|
sl@0
|
424 |
__RESTORE_REGS__
|
|
sl@0
|
425 |
__JUMP(,lr);
|
|
sl@0
|
426 |
}
|
|
sl@0
|
427 |
|
|
sl@0
|
428 |
#undef __SAVE_REGS__
|
|
sl@0
|
429 |
#undef __RESTORE_REGS__
|
|
sl@0
|
430 |
#undef __DO_RMW3_OP__
|
|
sl@0
|
431 |
#undef __COND_GE__
|
|
sl@0
|
432 |
#undef __COND_LT__
|
|
sl@0
|
433 |
|
|
sl@0
|
434 |
|
|
sl@0
|
435 |
#endif
|
|
sl@0
|
436 |
|
|
sl@0
|
437 |
// Second inclusion undefines temporaries
|
|
sl@0
|
438 |
#include "atomic_ops.h"
|