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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\common\arm\atomic_32_v6.h
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// 32 bit atomic operations on V6 and V6K processors
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// Also 8 and 16 bit atomic operations on V6K processors
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// Also 8, 16 and 32 bit load/store on all processors
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//
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//
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#include "atomic_ops.h"
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#if defined(__OP_LOAD__)
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,__DATA_SIZE__)(const volatile TAny* /*a*/)
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{
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// R0=a
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// return value in R0
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__LDR_INST__( ," r0, [r0] ");
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r1);
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__JUMP(,lr);
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}
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#elif defined(__OP_STORE__)
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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#ifdef __BARRIERS_NEEDED__
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// R0=a, R1=v
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// return value in R0 equal to v
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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__STR_INST__( ," r1, [r0] ");
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asm("mov r0, r1 ");
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=v
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// return value in R0 equal to v
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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__STR_INST__( ," r1, [r0] ");
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__LOCAL_DATA_MEMORY_BARRIER__(r12);
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asm("mov r0, r1 ");
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__JUMP(,lr);
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}
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#elif defined(__OP_RMW1__)
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#ifdef __OP_SWP__
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#define __SOURCE_REG__ 1
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#define __DO_PROCESSING__
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#else
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#define __SOURCE_REG__ 2
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#if defined(__OP_ADD__)
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#define __DO_PROCESSING__ asm("add r2, r0, r1 ");
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#elif defined(__OP_AND__)
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#define __DO_PROCESSING__ asm("and r2, r0, r1 ");
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#elif defined(__OP_IOR__)
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#define __DO_PROCESSING__ asm("orr r2, r0, r1 ");
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#elif defined(__OP_XOR__)
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#define __DO_PROCESSING__ asm("eor r2, r0, r1 ");
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#endif
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#endif
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#define __DO_RMW1_OP__ \
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asm("mov r12, r0 "); \
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asm("1: "); \
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__LDREX_INST__(0,12); \
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__DO_PROCESSING__ \
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__STREX_INST__(3,__SOURCE_REG__,12); \
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asm("cmp r3, #0 "); \
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asm("bne 1b ");
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__DO_RMW1_OP__
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=v
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// return value in R0
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__DO_RMW1_OP__
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__LOCAL_DATA_MEMORY_BARRIER__(r3);
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__JUMP(,lr);
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}
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#undef __DO_RMW1_OP__
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#undef __SOURCE_REG__
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#undef __DO_PROCESSING__
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#elif defined(__OP_CAS__)
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#define __DO_CAS_OP__ \
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__LDR_INST__( ," r12, [r1] "); \
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asm("1: "); \
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__LDREX_INST__(3,0); \
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asm("cmp r3, r12 "); \
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asm("bne 2f "); \
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__STREX_INST__(3,2,0); \
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asm("cmp r3, #0 "); \
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asm("bne 1b "); \
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asm("2: "); \
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__STR_INST__(ne, "r3, [r1] "); \
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asm("movne r0, #0 "); \
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asm("moveq r0, #1 ");
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,rel,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,rlx,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__DO_CAS_OP__
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,ord,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ TBool __fname__(__OPERATION__,acq,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ * /*q*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=q, R2=v
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// return value in R0
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__DO_CAS_OP__
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__LOCAL_DATA_MEMORY_BARRIER__(r3);
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__JUMP(,lr);
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}
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#undef __DO_CAS_OP__
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#elif defined(__OP_AXO__)
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#define __SAVE_REGS__ asm("str r4, [sp, #-4]! ");
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#define __RESTORE_REGS__ asm("ldr r4, [sp], #4 ");
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#define __DO_AXO_OP__ \
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asm("mov r12, r0 "); \
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asm("1: "); \
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__LDREX_INST__(0,12); \
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asm("and r4, r0, r1 "); \
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asm("eor r4, r4, r2 "); \
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__STREX_INST__(3,4,12); \
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asm("cmp r3, #0 "); \
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asm("bne 1b ");
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=u, R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=u, R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__SAVE_REGS__
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__DO_AXO_OP__
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__RESTORE_REGS__
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__JUMP(,lr);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=u, R2=v
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// return value in R0
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#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
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__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
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#endif
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}
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extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
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{
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// R0=a, R1=u, R2=v
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// return value in R0
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__SAVE_REGS__
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__DO_AXO_OP__
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__LOCAL_DATA_MEMORY_BARRIER__(r3);
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__RESTORE_REGS__
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__JUMP(,lr);
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}
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#undef __SAVE_REGS__
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#undef __RESTORE_REGS__
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#undef __DO_AXO_OP__
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#elif defined(__OP_RMW3__)
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#define __SAVE_REGS__ asm("stmfd sp!, {r4-r5} ");
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#define __RESTORE_REGS__ asm("ldmfd sp!, {r4-r5} ");
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#if defined(__OP_TAU__)
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#define __COND_GE__ "cs"
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#define __COND_LT__ "cc"
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#define __DO_SIGN_EXTEND__
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#elif defined(__OP_TAS__)
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#define __COND_GE__ "ge"
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#define __COND_LT__ "lt"
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#define __DO_SIGN_EXTEND__ __SIGN_EXTEND__(r0)
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#endif
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#define __DO_RMW3_OP__ \
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asm("mov r12, r0 "); \
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asm("1: "); \
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__LDREX_INST__(0,12); \
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__DO_SIGN_EXTEND__ \
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asm("cmp r0, r1 "); \
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asm("add" __COND_GE__ " r4, r0, r2 "); \
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asm("add" __COND_LT__ " r4, r0, r3 "); \
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274 |
__STREX_INST__(5,4,12); \
|
|
sl@0
|
275 |
asm("cmp r5, #0 "); \
|
|
sl@0
|
276 |
asm("bne 1b ");
|
|
sl@0
|
277 |
|
|
sl@0
|
278 |
|
|
sl@0
|
279 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rel,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
280 |
{
|
|
sl@0
|
281 |
// R0=a, R1=t, R2=u, R3=v
|
|
sl@0
|
282 |
// return value in R0
|
|
sl@0
|
283 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
284 |
__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
|
|
sl@0
|
285 |
#endif
|
|
sl@0
|
286 |
}
|
|
sl@0
|
287 |
|
|
sl@0
|
288 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,rlx,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
289 |
{
|
|
sl@0
|
290 |
// R0=a, R1=t, R2=u, R3=v
|
|
sl@0
|
291 |
// return value in R0
|
|
sl@0
|
292 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
293 |
__SAVE_REGS__
|
|
sl@0
|
294 |
__DO_RMW3_OP__
|
|
sl@0
|
295 |
__RESTORE_REGS__
|
|
sl@0
|
296 |
__JUMP(,lr);
|
|
sl@0
|
297 |
#endif
|
|
sl@0
|
298 |
}
|
|
sl@0
|
299 |
|
|
sl@0
|
300 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,ord,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
301 |
{
|
|
sl@0
|
302 |
// R0=a, R1=t, R2=u, R3=v
|
|
sl@0
|
303 |
// return value in R0
|
|
sl@0
|
304 |
#ifdef __BARRIERS_NEEDED__ // If no barriers, all ordering variants collapse to same function
|
|
sl@0
|
305 |
__LOCAL_DATA_MEMORY_BARRIER_Z__(r12);
|
|
sl@0
|
306 |
#endif
|
|
sl@0
|
307 |
}
|
|
sl@0
|
308 |
|
|
sl@0
|
309 |
extern "C" EXPORT_C __NAKED__ __TYPE__ __fname__(__OPERATION__,acq,__DATA_SIZE__)(volatile TAny* /*a*/, __TYPE__ /*t*/, __TYPE__ /*u*/, __TYPE__ /*v*/)
|
|
sl@0
|
310 |
{
|
|
sl@0
|
311 |
// R0=a, R1=t, R2=u, R3=v
|
|
sl@0
|
312 |
// return value in R0
|
|
sl@0
|
313 |
__SAVE_REGS__
|
|
sl@0
|
314 |
__DO_RMW3_OP__
|
|
sl@0
|
315 |
__LOCAL_DATA_MEMORY_BARRIER__(r5);
|
|
sl@0
|
316 |
__RESTORE_REGS__
|
|
sl@0
|
317 |
__JUMP(,lr);
|
|
sl@0
|
318 |
}
|
|
sl@0
|
319 |
|
|
sl@0
|
320 |
#undef __SAVE_REGS__
|
|
sl@0
|
321 |
#undef __RESTORE_REGS__
|
|
sl@0
|
322 |
#undef __DO_RMW3_OP__
|
|
sl@0
|
323 |
#undef __COND_GE__
|
|
sl@0
|
324 |
#undef __COND_LT__
|
|
sl@0
|
325 |
#undef __DO_SIGN_EXTEND__
|
|
sl@0
|
326 |
|
|
sl@0
|
327 |
|
|
sl@0
|
328 |
#endif
|
|
sl@0
|
329 |
|
|
sl@0
|
330 |
// Second inclusion undefines temporaries
|
|
sl@0
|
331 |
#include "atomic_ops.h"
|