# HG changeset patch
# User moel.mich
# Date 1372522360 0
# Node ID c9dfdbd59bf83fd37990818bed3737487adb0025
# Parent  3890d78140c23a582c81e51edd0378e7b35dfe8d
Added experimental support for AMD family 15h model 1Xh and family 16h CPUs.

diff -r 3890d78140c2 -r c9dfdbd59bf8 Hardware/CPU/AMD10CPU.cs
--- a/Hardware/CPU/AMD10CPU.cs	Tue Jun 25 20:34:29 2013 +0000
+++ b/Hardware/CPU/AMD10CPU.cs	Sat Jun 29 16:12:40 2013 +0000
@@ -4,7 +4,7 @@
   License, v. 2.0. If a copy of the MPL was not distributed with this
   file, You can obtain one at http://mozilla.org/MPL/2.0/.
  
-  Copyright (C) 2009-2011 Michael Möller <mmoeller@openhardwaremonitor.org>
+  Copyright (C) 2009-2013 Michael Möller <mmoeller@openhardwaremonitor.org>
 	
 */
 
@@ -13,7 +13,6 @@
 using System.Diagnostics;
 using System.Globalization;
 using System.IO;
-using System.Runtime.InteropServices;
 using System.Text;
 using System.Threading;
 
@@ -36,7 +35,10 @@
     private const ushort FAMILY_11H_MISCELLANEOUS_CONTROL_DEVICE_ID = 0x1303;
     private const ushort FAMILY_12H_MISCELLANEOUS_CONTROL_DEVICE_ID = 0x1703;
     private const ushort FAMILY_14H_MISCELLANEOUS_CONTROL_DEVICE_ID = 0x1703;
-    private const ushort FAMILY_15H_MISCELLANEOUS_CONTROL_DEVICE_ID = 0x1603; 
+    private const ushort FAMILY_15H_MODEL_00_MISC_CONTROL_DEVICE_ID = 0x1603;
+    private const ushort FAMILY_15H_MODEL_10_MISC_CONTROL_DEVICE_ID = 0x1403;
+    private const ushort FAMILY_16H_MODEL_00_MISC_CONTROL_DEVICE_ID = 0x1533;
+
     private const uint REPORTED_TEMPERATURE_CONTROL_REGISTER = 0xA4;
     private const uint CLOCK_POWER_TIMING_CONTROL_0_REGISTER = 0xD4;
 
@@ -67,8 +69,20 @@
           FAMILY_12H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
         case 0x14: miscellaneousControlDeviceId = 
           FAMILY_14H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
-        case 0x15: miscellaneousControlDeviceId =
-          FAMILY_15H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
+        case 0x15:
+          switch (model & 0xF0) {
+            case 0x00: miscellaneousControlDeviceId =
+              FAMILY_15H_MODEL_00_MISC_CONTROL_DEVICE_ID; break;
+            case 0x10: miscellaneousControlDeviceId =
+              FAMILY_15H_MODEL_10_MISC_CONTROL_DEVICE_ID; break;
+            default: miscellaneousControlDeviceId = 0; break;
+          } break;
+        case 0x16:
+          switch (model & 0xF0) {
+            case 0x00: miscellaneousControlDeviceId =
+              FAMILY_16H_MODEL_00_MISC_CONTROL_DEVICE_ID; break;            
+            default: miscellaneousControlDeviceId = 0; break;
+          } break;
         default: miscellaneousControlDeviceId = 0; break;
       }
 
@@ -220,7 +234,8 @@
       switch (family) {
         case 0x10:
         case 0x11: 
-        case 0x15: {
+        case 0x15: 
+        case 0x16: {
             // 8:6 CpuDid: current core divisor ID
             // 5:0 CpuFid: current core frequency ID
             uint cpuDid = (cofvidEax >> 6) & 7;
@@ -286,8 +301,17 @@
           if (Ring0.ReadPciConfig(miscellaneousControlAddress,
             REPORTED_TEMPERATURE_CONTROL_REGISTER, out value)) {
             if (family == 0x15 && (value & 0x30000) == 0x30000) {
-              coreTemperature.Value = ((value >> 21) & 0x7FC) / 8.0f +
-                coreTemperature.Parameters[0].Value - 49;
+              if ((model & 0xF0) == 0x00) {
+                coreTemperature.Value = ((value >> 21) & 0x7FC) / 8.0f +
+                  coreTemperature.Parameters[0].Value - 49;
+              } else {
+                coreTemperature.Value = ((value >> 21) & 0x7FF) / 8.0f +
+                  coreTemperature.Parameters[0].Value - 49;
+              }
+            } else if (family == 0x16 && 
+              ((value & 0x30000) == 0x30000 || (value & 0x80000) == 0x80000)) {
+                coreTemperature.Value = ((value >> 21) & 0x7FF) / 8.0f +
+                  coreTemperature.Parameters[0].Value - 49;
             } else {
               coreTemperature.Value = ((value >> 21) & 0x7FF) / 8.0f +
                 coreTemperature.Parameters[0].Value;
diff -r 3890d78140c2 -r c9dfdbd59bf8 Hardware/CPU/CPUGroup.cs
--- a/Hardware/CPU/CPUGroup.cs	Tue Jun 25 20:34:29 2013 +0000
+++ b/Hardware/CPU/CPUGroup.cs	Sat Jun 29 16:12:40 2013 +0000
@@ -4,7 +4,7 @@
   License, v. 2.0. If a copy of the MPL was not distributed with this
   file, You can obtain one at http://mozilla.org/MPL/2.0/.
  
-  Copyright (C) 2009-2011 Michael Möller <mmoeller@openhardwaremonitor.org>
+  Copyright (C) 2009-2013 Michael Möller <mmoeller@openhardwaremonitor.org>
 	
 */
 
@@ -101,6 +101,7 @@
               case 0x12:
               case 0x14:
               case 0x15:
+              case 0x16:
                 hardware.Add(new AMD10CPU(index, coreThreads, settings));
                 break;
               default:
diff -r 3890d78140c2 -r c9dfdbd59bf8 Properties/AssemblyVersion.cs
--- a/Properties/AssemblyVersion.cs	Tue Jun 25 20:34:29 2013 +0000
+++ b/Properties/AssemblyVersion.cs	Sat Jun 29 16:12:40 2013 +0000
@@ -10,5 +10,5 @@
 
 using System.Reflection;
 
-[assembly: AssemblyVersion("0.5.1.16")]
-[assembly: AssemblyInformationalVersion("0.5.1.16 Alpha")]
\ No newline at end of file
+[assembly: AssemblyVersion("0.5.1.18")]
+[assembly: AssemblyInformationalVersion("0.5.1.18 Alpha")]
\ No newline at end of file