Added initial support for AMD family 12h and 15h CPUs.
3 Version: MPL 1.1/GPL 2.0/LGPL 2.1
5 The contents of this file are subject to the Mozilla Public License Version
6 1.1 (the "License"); you may not use this file except in compliance with
7 the License. You may obtain a copy of the License at
9 http://www.mozilla.org/MPL/
11 Software distributed under the License is distributed on an "AS IS" basis,
12 WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
13 for the specific language governing rights and limitations under the License.
15 The Original Code is the Open Hardware Monitor code.
17 The Initial Developer of the Original Code is
18 Michael Möller <m.moeller@gmx.ch>.
19 Portions created by the Initial Developer are Copyright (C) 2009-2010
20 the Initial Developer. All Rights Reserved.
24 Alternatively, the contents of this file may be used under the terms of
25 either the GNU General Public License Version 2 or later (the "GPL"), or
26 the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
27 in which case the provisions of the GPL or the LGPL are applicable instead
28 of those above. If you wish to allow use of your version of this file only
29 under the terms of either the GPL or the LGPL, and not to allow others to
30 use your version of this file under the terms of the MPL, indicate your
31 decision by deleting the provisions above and replace them with the notice
32 and other provisions required by the GPL or the LGPL. If you do not delete
33 the provisions above, a recipient may use your version of this file under
34 the terms of any one of the MPL, the GPL or the LGPL.
39 using System.Globalization;
41 using System.Threading;
43 namespace OpenHardwareMonitor.Hardware.CPU {
44 internal sealed class AMD0FCPU : AMDCPU {
46 private readonly Sensor[] coreTemperatures;
47 private readonly Sensor[] coreClocks;
48 private readonly Sensor busClock;
50 private const uint FIDVID_STATUS = 0xC0010042;
52 private const byte MISCELLANEOUS_CONTROL_FUNCTION = 3;
53 private const ushort MISCELLANEOUS_CONTROL_DEVICE_ID = 0x1103;
54 private const uint THERMTRIP_STATUS_REGISTER = 0xE4;
56 private readonly byte thermSenseCoreSelCPU0;
57 private readonly byte thermSenseCoreSelCPU1;
58 private readonly uint miscellaneousControlAddress;
60 public AMD0FCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
61 : base(processorIndex, cpuid, settings)
63 float offset = -49.0f;
65 // AM2+ 65nm +21 offset
66 uint model = cpuid[0][0].Model;
67 if (model >= 0x69 && model != 0xc1 && model != 0x6c && model != 0x7c)
71 // AMD Athlon 64 Processors
72 thermSenseCoreSelCPU0 = 0x0;
73 thermSenseCoreSelCPU1 = 0x4;
75 // AMD NPT Family 0Fh Revision F, G have the core selection swapped
76 thermSenseCoreSelCPU0 = 0x4;
77 thermSenseCoreSelCPU1 = 0x0;
80 // check if processor supports a digital thermal sensor
81 if (cpuid[0][0].ExtData.GetLength(0) > 7 &&
82 (cpuid[0][0].ExtData[7, 3] & 1) != 0)
84 coreTemperatures = new Sensor[coreCount];
85 for (int i = 0; i < coreCount; i++) {
87 new Sensor("Core #" + (i + 1), i, SensorType.Temperature,
88 this, new [] { new ParameterDescription("Offset [°C]",
89 "Temperature offset of the thermal sensor.\n" +
90 "Temperature = Value + Offset.", offset)
94 coreTemperatures = new Sensor[0];
97 miscellaneousControlAddress = GetPciAddress(
98 MISCELLANEOUS_CONTROL_FUNCTION, MISCELLANEOUS_CONTROL_DEVICE_ID);
100 busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings);
101 coreClocks = new Sensor[coreCount];
102 for (int i = 0; i < coreClocks.Length; i++) {
103 coreClocks[i] = new Sensor(CoreString(i), i + 1, SensorType.Clock,
105 if (HasTimeStampCounter)
106 ActivateSensor(coreClocks[i]);
112 protected override uint[] GetMSRs() {
113 return new [] { FIDVID_STATUS };
116 public override string GetReport() {
117 StringBuilder r = new StringBuilder();
118 r.Append(base.GetReport());
120 r.Append("Miscellaneous Control Address: 0x");
121 r.AppendLine((miscellaneousControlAddress).ToString("X",
122 CultureInfo.InvariantCulture));
128 public override void Update() {
131 if (miscellaneousControlAddress != Ring0.InvalidPciAddress) {
132 for (uint i = 0; i < coreTemperatures.Length; i++) {
133 if (Ring0.WritePciConfig(
134 miscellaneousControlAddress, THERMTRIP_STATUS_REGISTER,
135 i > 0 ? thermSenseCoreSelCPU1 : thermSenseCoreSelCPU0)) {
137 if (Ring0.ReadPciConfig(
138 miscellaneousControlAddress, THERMTRIP_STATUS_REGISTER,
141 coreTemperatures[i].Value = ((value >> 16) & 0xFF) +
142 coreTemperatures[i].Parameters[0].Value;
143 ActivateSensor(coreTemperatures[i]);
145 DeactivateSensor(coreTemperatures[i]);
151 if (HasTimeStampCounter) {
152 double newBusClock = 0;
154 for (int i = 0; i < coreClocks.Length; i++) {
158 if (Ring0.RdmsrTx(FIDVID_STATUS, out eax, out edx,
159 1UL << cpuid[i][0].Thread)) {
160 // CurrFID can be found in eax bits 0-5, MaxFID in 16-21
161 // 8-13 hold StartFID, we don't use that here.
162 double curMP = 0.5 * ((eax & 0x3F) + 8);
163 double maxMP = 0.5 * ((eax >> 16 & 0x3F) + 8);
164 coreClocks[i].Value =
165 (float)(curMP * TimeStampCounterFrequency / maxMP);
166 newBusClock = (float)(TimeStampCounterFrequency / maxMP);
168 // Fail-safe value - if the code above fails, we'll use this instead
169 coreClocks[i].Value = (float)TimeStampCounterFrequency;
173 if (newBusClock > 0) {
174 this.busClock.Value = (float)newBusClock;
175 ActivateSensor(this.busClock);