1.1 --- a/Hardware/CPU/IntelCPU.cs	Thu Jan 20 21:48:26 2011 +0000
     1.2 +++ b/Hardware/CPU/IntelCPU.cs	Fri Jan 21 21:41:14 2011 +0000
     1.3 @@ -46,7 +46,8 @@
     1.4        Unknown,
     1.5        Core,
     1.6        Atom,
     1.7 -      Nehalem
     1.8 +      Nehalem,
     1.9 +      SandyBridge
    1.10      }
    1.11  
    1.12      private readonly Sensor[] coreTemperatures;
    1.13 @@ -68,6 +69,20 @@
    1.14        return result;
    1.15      }
    1.16  
    1.17 +    private float[] GetTjMaxFromMSR() {
    1.18 +      uint eax, edx;
    1.19 +      float[] result = new float[coreCount];
    1.20 +      for (int i = 0; i < coreCount; i++) {
    1.21 +        if (Ring0.RdmsrTx(IA32_TEMPERATURE_TARGET, out eax,
    1.22 +          out edx, 1UL << cpuid[i][0].Thread)) {
    1.23 +          result[i] = (eax >> 16) & 0xFF;
    1.24 +        } else {
    1.25 +          result[i] = 100;
    1.26 +        }
    1.27 +      }
    1.28 +      return result;
    1.29 +    }
    1.30 +
    1.31      public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
    1.32        : base(processorIndex, cpuid, settings) 
    1.33      {
    1.34 @@ -111,19 +126,17 @@
    1.35                  } break;
    1.36                case 0x1A: // Intel Core i7 LGA1366 (45nm)
    1.37                case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
    1.38 +              case 0x1F: // Intel Core i5, i7 
    1.39                case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
    1.40                case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
    1.41 +              case 0x2E: // Intel Xeon Processor 7500 series
    1.42                  microarchitecture = Microarchitecture.Nehalem;
    1.43 -                uint eax, edx;
    1.44 -                tjMax = new float[coreCount];
    1.45 -                for (int i = 0; i < coreCount; i++) {
    1.46 -                  if (Ring0.RdmsrTx(IA32_TEMPERATURE_TARGET, out eax,
    1.47 -                    out edx, 1UL << cpuid[i][0].Thread)) {
    1.48 -                    tjMax[i] = (eax >> 16) & 0xFF;
    1.49 -                  } else {
    1.50 -                    tjMax[i] = 100;
    1.51 -                  }
    1.52 -                }                
    1.53 +                tjMax = GetTjMaxFromMSR();
    1.54 +                break;
    1.55 +              case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm)
    1.56 +              case 0x2D: // Next Generation Intel Xeon Processor
    1.57 +                microarchitecture = Microarchitecture.SandyBridge;
    1.58 +                tjMax = GetTjMaxFromMSR();
    1.59                  break;
    1.60                default:
    1.61                  microarchitecture = Microarchitecture.Unknown;
    1.62 @@ -147,7 +160,8 @@
    1.63                  ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);
    1.64              }
    1.65            } break;
    1.66 -        case Microarchitecture.Nehalem: {
    1.67 +        case Microarchitecture.Nehalem: 
    1.68 +        case Microarchitecture.SandyBridge: {
    1.69              uint eax, edx;
    1.70              if (Ring0.Rdmsr(MSR_PLATFORM_INFO, out eax, out edx)) {
    1.71                timeStampCounterMultiplier = (eax >> 8) & 0xff;
    1.72 @@ -241,7 +255,9 @@
    1.73            {
    1.74              newBusClock = 
    1.75                TimeStampCounterFrequency / timeStampCounterMultiplier;
    1.76 -            if (microarchitecture == Microarchitecture.Nehalem) {
    1.77 +            if (microarchitecture == Microarchitecture.Nehalem ||
    1.78 +                microarchitecture == Microarchitecture.SandyBridge) 
    1.79 +            {
    1.80                uint multiplier = eax & 0xff;
    1.81                coreClocks[i].Value = (float)(multiplier * newBusClock);
    1.82              } else {