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Hardware/WinRing0.sys
author
moel.mich
Sat, 16 Apr 2011 19:26:20 +0000
changeset 273
2054d5dcb680
permissions
-rw-r--r--
A first correction for reading core and bus clocks on AMD family 14h CPUs.
moel@236
1
(binary:application/octet-stream)