OpenHardwareMonitor-retired: Hardware/CPU/IntelCPU.cs@35788ddd1825

     1 /*

     3   Version: MPL 1.1/GPL 2.0/LGPL 2.1

     5   The contents of this file are subject to the Mozilla Public License Version

     6   1.1 (the "License"); you may not use this file except in compliance with

     7   the License. You may obtain a copy of the License at

     9   http://www.mozilla.org/MPL/

    11   Software distributed under the License is distributed on an "AS IS" basis,

    12   WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License

    13   for the specific language governing rights and limitations under the License.

    15   The Original Code is the Open Hardware Monitor code.

    17   The Initial Developer of the Original Code is

    18   Michael Möller <m.moeller@gmx.ch>.

    19   Portions created by the Initial Developer are Copyright (C) 2009-2011

    20   the Initial Developer. All Rights Reserved.

    22   Contributor(s):

    24   Alternatively, the contents of this file may be used under the terms of

    25   either the GNU General Public License Version 2 or later (the "GPL"), or

    26   the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),

    27   in which case the provisions of the GPL or the LGPL are applicable instead

    28   of those above. If you wish to allow use of your version of this file only

    29   under the terms of either the GPL or the LGPL, and not to allow others to

    30   use your version of this file under the terms of the MPL, indicate your

    31   decision by deleting the provisions above and replace them with the notice

    32   and other provisions required by the GPL or the LGPL. If you do not delete

    33   the provisions above, a recipient may use your version of this file under

    34   the terms of any one of the MPL, the GPL or the LGPL.

    36 */

    38 using System;

    39 using System.Globalization;

    40 using System.Text;

    42 namespace OpenHardwareMonitor.Hardware.CPU {

    43   internal sealed class IntelCPU : GenericCPU {

    45     private enum Microarchitecture {

    46       Unknown,

    47       NetBurst,

    48       Core,

    49       Atom,

    50       Nehalem,

    51       SandyBridge

    52     }

    54     private readonly Sensor[] coreTemperatures;

    55     private readonly Sensor[] coreClocks;

    56     private readonly Sensor busClock;

    58     private readonly Microarchitecture microarchitecture;

    59     private readonly double timeStampCounterMultiplier;

    61     private const uint IA32_THERM_STATUS_MSR = 0x019C;

    62     private const uint IA32_TEMPERATURE_TARGET = 0x01A2;

    63     private const uint IA32_PERF_STATUS = 0x0198;

    64     private const uint MSR_PLATFORM_INFO = 0xCE;

    66     private float[] Floats(float f) {

    67       float[] result = new float[coreCount];

    68       for (int i = 0; i < coreCount; i++)

    69         result[i] = f;

    70       return result;

    71     }

    73     private float[] GetTjMaxFromMSR() {

    74       uint eax, edx;

    75       float[] result = new float[coreCount];

    76       for (int i = 0; i < coreCount; i++) {

    77         if (Ring0.RdmsrTx(IA32_TEMPERATURE_TARGET, out eax,

    78           out edx, 1UL << cpuid[i][0].Thread)) {

    79           result[i] = (eax >> 16) & 0xFF;

    80         } else {

    81           result[i] = 100;

    82         }

    83       }

    84       return result;

    85     }

    87     public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)

    88       : base(processorIndex, cpuid, settings)

    89     {

    90       // set tjMax

    91       float[] tjMax;

    92       switch (family) {

    93         case 0x06: {

    94             switch (model) {

    95               case 0x0F: // Intel Core 2 (65nm)

    96                 microarchitecture = Microarchitecture.Core;

    97                 switch (stepping) {

    98                   case 0x06: // B2

    99                     switch (coreCount) {

   100                       case 2:

   101                         tjMax = Floats(80 + 10); break;

   102                       case 4:

   103                         tjMax = Floats(90 + 10); break;

   104                       default:

   105                         tjMax = Floats(85 + 10); break;

   106                     }

   107                     tjMax = Floats(80 + 10); break;

   108                   case 0x0B: // G0

   109                     tjMax = Floats(90 + 10); break;

   110                   case 0x0D: // M0

   111                     tjMax = Floats(85 + 10); break;

   112                   default:

   113                     tjMax = Floats(85 + 10); break;

   114                 } break;

   115               case 0x17: // Intel Core 2 (45nm)

   116                 microarchitecture = Microarchitecture.Core;

   117                 tjMax = Floats(100); break;

   118               case 0x1C: // Intel Atom (45nm)

   119                 microarchitecture = Microarchitecture.Atom;

   120                 switch (stepping) {

   121                   case 0x02: // C0

   122                     tjMax = Floats(90); break;

   123                   case 0x0A: // A0, B0

   124                     tjMax = Floats(100); break;

   125                   default:

   126                     tjMax = Floats(90); break;

   127                 } break;

   128               case 0x1A: // Intel Core i7 LGA1366 (45nm)

   129               case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)

   130               case 0x1F: // Intel Core i5, i7

   131               case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)

   132               case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core

   133               case 0x2E: // Intel Xeon Processor 7500 series

   134                 microarchitecture = Microarchitecture.Nehalem;

   135                 tjMax = GetTjMaxFromMSR();

   136                 break;

   137               case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm)

   138               case 0x2D: // Next Generation Intel Xeon Processor

   139                 microarchitecture = Microarchitecture.SandyBridge;

   140                 tjMax = GetTjMaxFromMSR();

   141                 break;

   142               default:

   143                 microarchitecture = Microarchitecture.Unknown;

   144                 tjMax = Floats(100);

   145                 break;

   146             }

   147           } break;

   148         case 0x0F: {

   149             switch (model) {

   150               case 0x00: // Pentium 4 (180nm)

   151               case 0x01: // Pentium 4 (130nm)

   152               case 0x02: // Pentium 4 (130nm)

   153               case 0x03: // Pentium 4, Celeron D (90nm)

   154               case 0x04: // Pentium 4, Pentium D, Celeron D (90nm)

   155               case 0x06: // Pentium 4, Pentium D, Celeron D (65nm)

   156                 microarchitecture = Microarchitecture.NetBurst;

   157                 tjMax = Floats(100);

   158                 break;

   159               default:

   160                 microarchitecture = Microarchitecture.Unknown;

   161                 tjMax = Floats(100);

   162                 break;

   163             }

   164           } break;

   165         default:

   166           microarchitecture = Microarchitecture.Unknown;

   167           tjMax = Floats(100);

   168           break;

   169       }

   171       // set timeStampCounterMultiplier

   172       switch (microarchitecture) {

   173         case Microarchitecture.NetBurst:

   174         case Microarchitecture.Atom:

   175         case Microarchitecture.Core: {

   176             uint eax, edx;

   177             if (Ring0.Rdmsr(IA32_PERF_STATUS, out eax, out edx)) {

   178               timeStampCounterMultiplier =

   179                 ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);

   180             }

   181           } break;

   182         case Microarchitecture.Nehalem:

   183         case Microarchitecture.SandyBridge: {

   184             uint eax, edx;

   185             if (Ring0.Rdmsr(MSR_PLATFORM_INFO, out eax, out edx)) {

   186               timeStampCounterMultiplier = (eax >> 8) & 0xff;

   187             }

   188           } break;

   189         default: {

   190             timeStampCounterMultiplier = 1;

   191             uint eax, edx;

   192             if (Ring0.Rdmsr(IA32_PERF_STATUS, out eax, out edx)) {

   193               timeStampCounterMultiplier =

   194                 ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);

   195             }

   196           } break;

   197       }

   199       // check if processor supports a digital thermal sensor

   200       if (cpuid[0][0].Data.GetLength(0) > 6 &&

   201         (cpuid[0][0].Data[6, 0] & 1) != 0) {

   202         coreTemperatures = new Sensor[coreCount];

   203         for (int i = 0; i < coreTemperatures.Length; i++) {

   204           coreTemperatures[i] = new Sensor(CoreString(i), i,

   205             SensorType.Temperature, this, new [] {

   206               new ParameterDescription(

   207                 "TjMax [°C]", "TjMax temperature of the core.\n" +

   208                 "Temperature = TjMax - TSlope * Value.", tjMax[i]),

   209               new ParameterDescription("TSlope [°C]",

   210                 "Temperature slope of the digital thermal sensor.\n" +

   211                 "Temperature = TjMax - TSlope * Value.", 1)}, settings);

   212           ActivateSensor(coreTemperatures[i]);

   213         }

   214       } else {

   215         coreTemperatures = new Sensor[0];

   216       }

   218       busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings);

   219       coreClocks = new Sensor[coreCount];

   220       for (int i = 0; i < coreClocks.Length; i++) {

   221         coreClocks[i] =

   222           new Sensor(CoreString(i), i + 1, SensorType.Clock, this, settings);

   223         if (HasTimeStampCounter)

   224           ActivateSensor(coreClocks[i]);

   225       }

   227       Update();

   228     }

   230     protected override uint[] GetMSRs() {

   231       return new [] {

   232         MSR_PLATFORM_INFO,

   233         IA32_PERF_STATUS ,

   234         IA32_THERM_STATUS_MSR,

   235         IA32_TEMPERATURE_TARGET

   236       };

   237     }

   239     public override string GetReport() {

   240       StringBuilder r = new StringBuilder();

   241       r.Append(base.GetReport());

   243       r.Append("Microarchitecture: ");

   244       r.AppendLine(microarchitecture.ToString());

   245       r.Append("Time Stamp Counter Multiplier: ");

   246       r.AppendLine(timeStampCounterMultiplier.ToString(

   247         CultureInfo.InvariantCulture));

   248       r.AppendLine();

   250       return r.ToString();

   251     }

   253     public override void Update() {

   254       base.Update();

   256       for (int i = 0; i < coreTemperatures.Length; i++) {

   257         uint eax, edx;

   258         if (Ring0.RdmsrTx(

   259           IA32_THERM_STATUS_MSR, out eax, out edx,

   260             1UL << cpuid[i][0].Thread)) {

   261           // if reading is valid

   262           if ((eax & 0x80000000) != 0) {

   263             // get the dist from tjMax from bits 22:16

   264             float deltaT = ((eax & 0x007F0000) >> 16);

   265             float tjMax = coreTemperatures[i].Parameters[0].Value;

   266             float tSlope = coreTemperatures[i].Parameters[1].Value;

   267             coreTemperatures[i].Value = tjMax - tSlope * deltaT;

   268           } else {

   269             coreTemperatures[i].Value = null;

   270           }

   271         }

   272       }

   274       if (HasTimeStampCounter) {

   275         double newBusClock = 0;

   276         uint eax, edx;

   277         for (int i = 0; i < coreClocks.Length; i++) {

   278           System.Threading.Thread.Sleep(1);

   279           if (Ring0.RdmsrTx(IA32_PERF_STATUS, out eax, out edx,

   280             1UL << cpuid[i][0].Thread))

   281           {

   282             newBusClock =

   283               TimeStampCounterFrequency / timeStampCounterMultiplier;

   284             switch (microarchitecture) {

   285               case Microarchitecture.Nehalem: {

   286                   uint multiplier = eax & 0xff;

   287                   coreClocks[i].Value = (float)(multiplier * newBusClock);

   288                 } break;

   289               case Microarchitecture.SandyBridge: {

   290                   uint multiplier = (eax >> 8) & 0xff;

   291                   coreClocks[i].Value = (float)(multiplier * newBusClock);

   292                 } break;

   293               default: {

   294                   double multiplier =

   295                     ((eax >> 8) & 0x1f) + 0.5 * ((eax >> 14) & 1);

   296                   coreClocks[i].Value = (float)(multiplier * newBusClock);

   297                 } break;

   298             }

   299           } else {

   300             // if IA32_PERF_STATUS is not available, assume TSC frequency

   301             coreClocks[i].Value = (float)TimeStampCounterFrequency;

   302           }

   303         }

   304         if (newBusClock > 0) {

   305           this.busClock.Value = (float)newBusClock;

   306           ActivateSensor(this.busClock);

   307         }

   308       }

   309     }

   310   }

   311 }

author	moel.mich
	Sat, 30 Apr 2011 16:03:58 +0000
changeset 275	35788ddd1825
parent 250	c19d56a0bcad
child 306	e9127c00ada1
permissions	-rw-r--r--