A first correction for reading core and bus clocks on AMD family 14h CPUs.
3 Version: MPL 1.1/GPL 2.0/LGPL 2.1
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6 1.1 (the "License"); you may not use this file except in compliance with
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15 The Original Code is the Open Hardware Monitor code.
17 The Initial Developer of the Original Code is
18 Michael Möller <m.moeller@gmx.ch>.
19 Portions created by the Initial Developer are Copyright (C) 2009-2010
20 the Initial Developer. All Rights Reserved.
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25 either the GNU General Public License Version 2 or later (the "GPL"), or
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38 namespace OpenHardwareMonitor.Hardware.CPU {
40 internal abstract class AMDCPU : GenericCPU {
42 private const byte PCI_BUS = 0;
43 private const byte PCI_BASE_DEVICE = 0x18;
44 private const byte DEVICE_VENDOR_ID_REGISTER = 0;
45 private const ushort AMD_VENDOR_ID = 0x1022;
47 public AMDCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
48 : base(processorIndex, cpuid, settings) { }
50 protected uint GetPciAddress(byte function, ushort deviceId) {
52 // assemble the pci address
53 uint address = Ring0.GetPciAddress(PCI_BUS,
54 (byte)(PCI_BASE_DEVICE + processorIndex), function);
56 // verify that we have the correct bus, device and function
58 if (!Ring0.ReadPciConfig(
59 address, DEVICE_VENDOR_ID_REGISTER, out deviceVendor))
60 return Ring0.InvalidPciAddress;
62 if (deviceVendor != (deviceId << 16 | AMD_VENDOR_ID))
63 return Ring0.InvalidPciAddress;